174 engineer digital design engineering jobs at 88 companies in Benicia, CA
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Senior Digital Design Engineer
Vancouver or Chandler or San Francisco
$150k-$200k/yr HybridFull Time
6+ YOEBachelor's or master's degree in electrical or computer engineering, 6+ years of digital IC design experience, and hands-on Verilog or SystemVerilog RTL development for complex SoCs or ASICs.
Verilog, SystemVerilog, Synopsys, Cadence, SDC, UPF, CPF
1mo
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Digital Layout Design Engineer
Santa Clara, California, United States
OnsiteFull Time
Design custom digital macros and libraries for ASICs at advanced technology nodes; collaborate with integration, CAD, circuit, and technology engineering teams.
1w
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PMTS ASIC Digital Design IP ENGINEERING
Santa Clara, California, United States
$167k-$275k/yr OnsiteFull Time
12+ YOEBachelor's or master's degree in electrical or computer engineering, 12+ years of processor or complex SoC digital design, expert Verilog/SystemVerilog, and expertise in microarchitecture, synthesis, timing, CDC, RDC, and low-power design.
Verilog, SystemVerilog, RISC-V, ARM, MIPS, ARC, ISO 26262, DO-254, EDA
1w
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PMTS ASIC Digital Design IP ENGINEERING
Santa Clara, California, United States
$167k-$275k/yr OnsiteFull Time
12+ YOEBachelor's or master's degree in electrical or computer engineering; 12+ years in processor, CPU, DSP, or complex SoC digital design; expert Verilog/SystemVerilog and processor microarchitecture expertise.
Verilog, SystemVerilog, EDA
1mo
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AI Silicon, Digital Design Engineer
Palo Alto, California, United States
OnsiteFull Time
8+ YOEB.S. or M.S. in EE/Computer Engineering, 8+ years ASIC/SoC digital design experience, Verilog RTL expertise, EDA tool proficiency, synthesis/timing/LEC experience, and mentorship/communication skills.
Verilog, RTL, EDA tools, Logical Equivalence Checking (LEC), Clock Domain Crossing (CDC), Reset Domain Crossing (RDC)
2mo
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
5+ YOE5+ years experience in digital/ASIC design, degree in EE/CE or equivalent, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), RTL implementation, and ASIC design flows.
NVLink, PCI-Express, Ethernet, UCIE, RTL
1mo
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Digital IC Design Engineer | BCP
Santa Clara, California, United States
$130k-$241k/yr OnsiteFull Time
3+ YOEB.S. in Electrical Engineering, 3+ years digital design experience; RTL/Verilog/SystemVerilog, Cadence, Python, UVM, and GDSII experience preferred; ability to implement and verify synthesizable RTL to GDSII.
RTL, Verilog/Systemverilog, Cadence, Python, UVM, VAMS, GDSII
1mo
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Machine Learning Digital Design Engineer
Sunnyvale, California, United States
$178k-$250k/yr OnsiteFull Time
8+ YOEBachelor's degree or equivalent, 8+ years hardware design experience for production silicon, expertise in digital µarchitecture, RTL coding, micro-architecture development, and cross-functional technical communication.
RTL, SoC, ASIC, DSP, microcontrollers
1mo
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Technical Staff Engineer - Digital Design
San Jose, California, United States
$70k-$143k/yr HybridFull Time
12+ YOEBachelor's in EE/CE, 12+ years relevant experience (10+ in FPGA/ASIC IP and system design), VHDL/Verilog expertise, FPGA design/verification experience, strong digital design and architecture knowledge, excellent communication; US citizenship or permanent residency required.
VHDL, Verilog, Libero, Quartus, Vivado, Identify Debugger, SignalTap, ChipScope, ModelSim, QuestaSim, Python, TCL
1mo
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Senior Staff Engineer, Digital IC Design
Santa Clara, California, United States
$134k-$201k/yr OnsiteFull Time
5+ YOEDegree in computer or electrical engineering with 3–5+ years SOC/SoC experience, RTL design in SystemVerilog, SoC integration and timing closure, CDC/clock/reset design, and scripting with Python or Tcl.
SystemVerilog, Python, Tcl
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Senior RTL Design Engineer, Digital Signal Processing
Sunnyvale, California, United States
$163k-$236k/yr OnsiteFull Time
8+ YOEBachelor's degree in electrical or computer engineering, 8 years of DSP or high-speed digital logic design, and experience with communication systems, PHY, MATLAB, Python, or C++.
MATLAB, Python, C++, Design Compiler, Genus, PrimeTime, Tempus, Spyglass, Conformal, SerDes, SystemC
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Design Engineer III
Menlo Park or Sunnyvale
$140k-$150k/yr HybridFull Time
5+ YOERequires a BS in electrical/computer engineering or computer science, 5+ years of experience, SystemVerilog/UVM verification, coverage and SVA, RTL debug, simulators, Python or Perl, and digital design fundamentals.
SystemVerilog, UVM, VCS, Xcelium, Questa, Verdi, Python, Perl, PrimeTime PX (PTPX), PrimePower, UPF, Palladium, Zebu, RTL-to-GDSII
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Senior Design Engineer
Mountain View or Redmond
$120k-$235k/yr HybridFull Time
5+ YOERequires a doctorate plus 1+ year, master's plus 4+ years, bachelor's plus 5+ years, or equivalent experience in electrical, computer, or related engineering. Preferred expertise includes digital design, RTL, NoC, ASIC/SoC, synthesis, and post-silicon debug.
Intellectual Property (IP), Register Transfer Level (RTL), System on Chip (SOC), Verilog, SystemVerilog, Clock Domain Crossing (CDC), NoCs, ASIC, CPU
2mo
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SoC Design Engineer
Santa Clara, California, United States
$157k-$160k/yr OnsiteFull Time
1+ YOEMaster's in Electrical or Computer Engineering required, 1+ year digital design experience; RTL/Verilog, SystemVerilog/SVA, Python, Perl; experience with Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator; FPGA prototyping, STA, DFT.
Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator, SystemVerilog, SVA, Python, Perl, Verilog, FPGA
2mo
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Electrical Design Engineer
Palo Alto, California, United States
$130k-$179k/yr HybridFull Time
7+ YOEBS/MS in Electrical Engineering; 7+ years PCB design experience; strong analog/digital/power circuitry; EMI/SI knowledge; lab test experience; good communication.
PSpice, LTSpice, Hyperlynx, Oscilloscopes, Logic analyzers, PCB design tools, PCB layout constraints
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Hardware Design Engineer
Tempe or San Jose or San Francisco or New York City
$133k-$210k/yr OnsiteFull Time
4+ YOEBachelor's degree or equivalent in electrical or computer engineering, 4+ years in high-speed digital board design and FPGA/RTL development, US citizenship, Secret clearance eligibility, and up to 10% travel.
SystemVerilog, Verilog, VHDL, AMD Vivado, Intel Quartus, Synopsys Synplify, Mentor Xpedition, Cadence, Altium, HyperLynx, Python, TCL, Perl, ModelSim, Questa, Git, Claude Code, Copilot, DDR4, SERDES, UART, I2C, SPI, LVDS, FPGA, RTL, SoC, ADC, DAC, CI/CD, AI
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Design Verification Engineer- CPU
Santa Clara, California, United States
$200k-$350k/yr OnsiteFull Time
8+ YOE8+ years verifying high-performance CPUs or complex digital designs; SystemVerilog, UVM, C, C++, assertions, coverage, testbench, and debugging experience; BS+ in engineering or computer science.
SystemVerilog, UVM, C, C++, ARM, RISC-V, FPGA
1mo
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Senior Logic Design Engineer
Sunnyvale, California, United States
$170k-$250k/yr OnsiteFull Time
10+ YOEBachelor's in Electrical/Computer Engineering, 10+ years front-end digital SoC experience, Verilog/SystemVerilog and synthesis expertise, embedded/mixed-mode design and strong debugging and communication skills.
Verilog, SystemVerilog
3mo
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PCB Design Engineer – Altium / Schematic & Layout
Saratoga, California, United States
$130k-$200k/yr OnsiteFull Time
PCB design engineer with Altium, multi-layer high-speed digital/mixed-signal boards; DFx focus; not RF design.
Altium Designer
2mo
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Senior Hardware Design Engineer
Newark, California, United States
$130k-$150k/yr OnsiteFull Time
10+ YOEBachelor's in electrical engineering, 10+ years designing high-speed digital/analog circuitry and complex high-density PCBs, 5+ years designing fine-pitch boards, hands-on validation and debugging, proficiency with Python and C, experience with DDR4/DDR5 and PCIe Gen 5/6.
Python, C, DDR4, DDR5, PCIe Gen 5/6, SERDES, Protocol Analyzers, Oscilloscopes, Logic Analyzers, EVT, DVT