Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
98 engineer digital design engineering jobs at 38 companies in Pacific Grove, CA
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Digital Design Engineer
San Jose, California, United States
$166k-$229k/yr OnsiteFull Time
Master's degree in electrical, electronics, or computer engineering required. Requires C/C++ or Python, Verilog, VLSI design, signal processing, digital and analog IC design, design automation, and computer architecture knowledge.
C, C++, Python, Verilog
3d
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Associate Digital Design Engineer
San Jose, California, United States
$86k-$118k/yr OnsiteFull Time
0+ YOEBachelor's or master's degree in electrical or computer engineering preferred; 0–2 years' digital design experience; Verilog/SystemVerilog, RTL, simulation, verification, synthesis, and analytical skills.
Verilog, SystemVerilog, RTL, Python, Perl, Tcl, Shell
1mo
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Digital Design Engineer
San Jose, California, United States
$130k-$200k/yr OnsiteFull Time
5+ YOEBS/MS/PhD in EE/CE,5+ years digital RTL design experience,SystemVerilog proficiency,ASIC flow and EDA tool experience,high-speed SerDes/DSP knowledge,Python/MATLAB/C++ familiarity.
System Verilog, Synopsys, Cadence, Siemens, Python, MATLAB, C++
3w
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Senior HSIO Digital Design Engineer
San Jose, California, United States
$138k-$206k/yr OnsiteFull Time
3+ YOE3+ years industry experience in digital HSIO or die-to-die interfaces; BS/MS/PhD in Electrical Engineering with specified experience; knowledge of high-speed serial protocols, SI/PI, and digital/analog co-design.
AXI, CHI, CXS.B, CXL, PCIE, UA-Link
1mo
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Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOEBSEE required; 8+ years experience in SoC integration with RTL design in advanced nodes, SystemVerilog proficiency, PPA/CDC/RDC and low-power design knowledge; EMR not mentioned.
SystemVerilog
1mo
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Principal Digital Design Engineer
San Jose, California, United States
$190k-$240k/yr HybridFull Time
8+ YOEMS/PhD EE with 8+ years or BS EE with 12+ years; SOC architecture experience, bus/interface protocols, embedded memory knowledge, RTL/DFT/synthesis flow, silicon bring-up, strong communication and team skills.
AHB, APB, AXI, USB, I2C, I3C, SPI, UART, SRAM, OTP, MTP, EE/Flash, DDR DRAM, Flash
3w
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ASIC Digital Design Engineer Lead
Cupertino, California, United States
OnsiteFull Time
Senior-level engineering leadership to drive technical engagements with suppliers, define and productize custom silicon, and communicate across multifunctional teams.
2mo
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ASIC Digital Design, Sr Staff Engineer
Noida or Bangalore or San Jose
OnsiteFull Time
8+ YOEBSEE/MSEE with 8+ years ASIC digital design experience; expertise in UCIe/PCIe/DDR/CXL/USB, SystemVerilog/Verilog, synthesis, CDC, formal, STA, Fusion Compiler, Perforce, and scripting (Perl/Shell).
SystemVerilog, Verilog, Fusion Compiler, Perforce, Perl, Shell
1mo
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Design Engineer
San Jose, California, United States
OnsiteFull Time
3+ YOEBS/MS in Electrical/Computer Engineering (or equivalent), 3+ years SystemVerilog RTL design experience, strong digital design fundamentals, power/timing-aware practices, simulation debug, and scripting in Python/Perl/TCL.
SystemVerilog, Python, Perl, TCL, UVM, SVA
1w
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Design Engineer (7848)
San Jose, California, United States
$156k-$156k/yr OnsiteFull Time
Master’s degree in electrical or computer engineering required. Experience with RTL, digital design, physical implementation, design verification, Perl, TCL, N16 technology, EDA tools, and semiconductor design flows.
Perl, TCL, EDA, RTL, DRC, LVS, ERC, P&R
1mo
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Sr. Staff/Staff Engineer, Digital Design
San Diego or San Jose
OnsiteFull Time
Deep RTL/SystemVerilog expertise, SoC architecture knowledge, familiarity with AXI/AHB/APB/OBI, multi-clock/multi-power-domain and timing closure experience, skills with SystemVerilog, Python, Tcl, UPF, and security technologies (Arm TrustZone, Secure Boot, PSA Level 2+); MS/PhD preferred.
SystemVerilog, Python, Tcl, UPF, AXI, AHB, APB, OBI, Arm TrustZone
2mo
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Principal Design Engineer
San Jose, California, United States
$198k-$336k/yr OnsiteFull Time
10+ YOEMS in Electrical Engineering or equivalent with 10+ years ASIC design experience; expertise in Verilog/SystemVerilog; knowledge of full digital ASIC design flow; experience with Design Compiler and PrimeTime; Python and AI-assisted tool familiarity.
Verilog, SystemVerilog, Design Compiler, PrimeTime, ncsim, Formality, Python
1mo
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Digital Design Specialist: Structural Engineering
San Jose, California, United States
$74k-$99k/yr HybridFull Time
4+ YOE4+ years experience in structural drafting/BIM, proficiency in CAD and Revit, strong communication, attention to detail, ability to produce construction documentation.
CAD, Revit, BIM
2mo
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Director Silicon Design Engineering
San Jose, California, United States
HybridFull Time
15+ YOE5+ Mgmt15+ years ASIC/semiconductor leadership; strong hands-on design and program management; FPGA experience a plus; deep ASIC development lifecycle knowledge.
RTL, ASIC, Analog Design, Digital Design, Tapeout, Post-Silicon Validation
2w
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Tech Lead Design Engineer
San Jose, California, United States
$133k-$185k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical or computer engineering, 5+ years of digital design experience, full-chip tapeout experience, and proficiency in Verilog/SystemVerilog, RTL, synthesis, timing closure, CDC, lint, and low-power design.
Verilog, SystemVerilog, PCIe, CXL, Ethernet, NVLink, UALink, COSMOS, UCIe, BIST
1w
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Hardware Design Engineer
Tempe or San Jose or San Francisco or New York City
$133k-$210k/yr OnsiteFull Time
4+ YOEBachelor's degree or equivalent in electrical or computer engineering, 4+ years in high-speed digital board design and FPGA/RTL development, US citizenship, Secret clearance eligibility, and up to 10% travel.
SystemVerilog, Verilog, VHDL, AMD Vivado, Intel Quartus, Synopsys Synplify, Mentor Xpedition, Cadence, Altium, HyperLynx, Python, TCL, Perl, ModelSim, Questa, Git, Claude Code, Copilot, DDR4, SERDES, UART, I2C, SPI, LVDS, FPGA, RTL, SoC, ADC, DAC, CI/CD, AI
4d
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Design Verification Engineer
San Jose, California, United States
$120k-$200k/yr OnsiteFull Time
5+ YOEBachelor's degree in computer science, computer engineering, or related field; 5+ years' relevant experience; strong SystemVerilog and UVM proficiency; digital design, SoC architecture, verification, scripting, and simulation debugging expertise.
SystemVerilog, UVM, Python, Perl, TCL, shell scripting, Claude
2w
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DFT Design Engineer
Austin or San Jose
OnsiteFull Time
3+ YOE3-12 years SoC/ASIC digital design experience with focus on DFT, scan insertion, compression scan, MBIST, ATPG, EMR not required. US citizenship preferred.
Cadence, Verilog, ATPG, MBIST, JTAG 1149.1, JTAG 1149.6, IEEE1500, IEEE1687
1mo
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SoC Digital Design Engineer, Multimedia Lab
San Jose, California, United States
$156k-$317k/yr OnsiteFull Time
1+ YOEBachelor's in EE/CS or related, 1+ years front-end digital design, mastery of Verilog/SystemVerilog, experience with front-end EDA tools, scripting (Python/Perl/Tcl/Makefile).
Verilog, SystemVerilog, Spyglass, Design Compiler, PrimeTime, Python, Perl, Tcl, Makefile, UPF, SDC, STA, FPGA, ASIC
2mo
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Principal Engineer - Digital ASIC Design
San Jose, California, United States
$70k-$163k/yr OnsiteFull Time
10+ YOE10+ years ASIC/FPGA digital design; SystemVerilog; Cadence/Synopsys front-end; PHY/Serdes knowledge; post-silicon validation; travel up to 25%.
System Verilog, Cadence Tools, Synopsys Tools, VCS, SpyGlass, Design Compiler, PrimeTime, Lab equipment