100 engineer digital design engineering jobs at 46 companies in San Marcos, TX
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Digital Layout Design Engineer
Austin, Texas, United States
OnsiteFull Time
Design custom digital layouts for ASICs, create digital macros and libraries, and collaborate with integration, CAD, circuit, and technology engineers.
CAD
2mo
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Digital Design Engineer I
Austin, Texas, United States
$79k-$146k/yr HybridFull Time
Degree in electrical/computer engineering or related field, academic/project experience in VLSI or digital IC design, knowledge of RTL, finite state machines, timing, Verilog/SystemVerilog, strong debugging and communication skills.
Verilog, SystemVerilog, EDA tools, simulation tools, verification environments
2mo
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Digital Design Engineer I
Austin, Texas, United States
$79k-$146k/yr HybridFull Time
Bachelor's degree in EE/CE or related field, academic/project experience in VLSI or digital IC design, familiarity with RTL design and Verilog/SystemVerilog, strong problem-solving and collaboration skills.
Verilog, SystemVerilog, EDA tools, simulation tools
2mo
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
5+ YOE5+ years experience in digital/ASIC design, degree in EE/CE or equivalent, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), RTL implementation, and ASIC design flows.
NVLink, PCI-Express, Ethernet, UCIE, RTL
1mo
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Senior Digital Design Engineer
Rochester or Austin or Herndon
$105k-$231k/yr OnsiteFull Time
10+ YOEBachelor's in EE,10+ years digital electronics design experience, PCB and high-speed digital expertise, proficiency with interfaces/protocols, lab test equipment experience, strong communication skills; U.S. citizenship required.
Siemens PADS, VHDL, Verilog, USB3.x, Ethernet, PCIe, I2C, SPI, Logic Analyzer, Signal Generator, Oscilloscope, Protocol Analyzer, Spectrum Analyzer, Network Analyzer
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Digital Design
Austin, Texas, United States
$119k/yr OnsiteFull Time
Master’s degree in electrical, electronics, or computer engineering; knowledge of Python, C/C++, Verilog, SystemVerilog, UVM, functional verification, computer architecture, RTL design, and digital systems.
Python, C, C++, Verilog, SystemVerilog, UVM, Synopsis Design Vision, RTL, Lint, LEC, CDC, STA, RDC
2mo
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Hardware Digital Engineer (PCB Design)
Austin, Texas, United States
HybridFull Time
5+ YOEBachelor's in Electrical, Computer, or Software Engineering; 5+ years digital hardware design; VHDL/SystemVerilog; FPGA; schematic capture; PCB layout; relocation to Austin; US work authorization without sponsorship.
VHDL, SystemVerilog, Schematic Capture, PCB Design Tools, FPGA
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ASIC Digital Design Engineer (HPC IP)
Austin, Texas, United States
$114k-$170k/yr OnsiteFull Time
5+ YOEBSEE or MSEE and 5+ years in ASIC digital design and verification, with RTL expertise, EDA tools, interface protocols, analytical problem-solving, and cross-functional communication skills.
RTL, Electronic Design Automation (EDA), PCI Express (PCIe), Compute Express Link (CXL), DDR, Ethernet
2mo
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Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
10+ YOEBS/MS in EE, 10+ years digital CMOS IC design experience, Verilog/System Verilog expertise, low-power (UPF/CPF) and clocking/CDC/RDC knowledge, AXI/AHB/APB experience, scripting (Python/Perl/Tcl), and leadership of small design teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, C, Python, Perl, Tcl, Perforce, Git, Methodics
2mo
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Sr. Staff Engineer - Digital Design Verification
Austin, Texas, United States
OnsiteFull Time
8+ YOEBSEE or MSEE with 8+ years verifying complex SoC digital designs using SystemVerilog/UVM and C/C++; proven tape-outs, SoC-level verification, and strong collaboration and debugging skills.
SystemVerilog, UVM, Verilog, C/C++, Python, Perl, Makefile
2mo
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Digital Design Verification Engineer
Bristol or Austin
£125k/yr OnsiteFull Time
5+ YOE5+ years in digital verification for high-performance ASICs/SoCs; strong SystemVerilog, SVA, UVM, Cocotb, formal verification, CDC/RDC, and algorithm modelling (MATLAB/Simulink or Python/NumPy) skills; experience with high-speed IP (SerDes, DDR/HBM, PCIe).
SystemVerilog, UVM, SVA, CocoTB, MATLAB/Simulink, Python, NumPy, Jasper, FPGA, RTL simulation, formal verification, linting, CDC/RDC, STA, UPF, CPF, gate-level simulation
2mo
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Senior Design Engineer
Austin, Texas, United States
$162k-$219k/yr HybridFull Time
7+ YOEBachelors/Masters in CS/ECE,7+ years designing complex SoC/compute subsystems,strong digital hardware design and Verilog experience,PCIe/DDR/HBM/UCIe integration,RTL development and SoC design methodologies.
Verilog, Perl, Python, SystemVerilog, UVM, OVM, PCIe, DDR, HBM, UCIe, Ethernet
1mo
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Lead FPGA Design Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBachelor’s degree in a related technical field and 5–10 years of FPGA or platform engineering experience. Requires FPGA design, RTL, verification, timing, lab debugging, and digital interface expertise.
FPGA, RTL, AMD/Xilinx, Intel/Altera, SPI, I2C, UART, Ethernet, PCIe, JESD, digital oscilloscopes, logic analyzers, function generators, printed circuit boards (PCBs)
2w
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DFT Design Engineer
Austin or San Jose
OnsiteFull Time
3+ YOE3-12 years SoC/ASIC digital design experience with focus on DFT, scan insertion, compression scan, MBIST, ATPG, EMR not required. US citizenship preferred.
Cadence, Verilog, ATPG, MBIST, JTAG 1149.1, JTAG 1149.6, IEEE1500, IEEE1687
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Senior RTL Design Engineer
Austin or San Jose
$120k-$200k/yr OnsiteFull Time
5+ YOEBachelor's degree in EE, computer engineering, or computer science; 5+ years of ASIC RTL design experience; SystemVerilog, architecture, digital logic, synthesis, timing analysis, verification tools, Python, and Linux shell skills.
SystemVerilog, AXI, PCIe, Ethernet, HBM, DDR, Python, Linux shell, Git, FPGA
2mo
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Digital Modem Engineer
Austin or Chicago or New York City or London
$150k-$250k/yr OnsiteFull Time
5+ YOE5+ years in digital modem design, modeling, and implementation; strong FPGA/ASIC knowledge; Python/C/C++/Matlab; MS/PhD in EE/CS or equivalent.
Python, C++, C, Matlab
2mo
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VLSI Design Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years ASIC/VLSI digital design experience; strong Verilog/SystemVerilog; familiarity with simulation and verification methodologies, synthesis/timing analysis, and protocol implementation; BS/MS in EE/CE.
Verilog, SystemVerilog, Python, Perl, TCL, EDA tools, SDC, CDC, Linting, Formal Verification
2mo
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Interconnect Micro-architect/RTL Design Engineer
Austin or Boxborough
$156k-$268k/yr HybridFull Time
Experienced RTL design engineer with strong Verilog/System Verilog skills, knowledge of C/C++ and scripting (Perl or Python), digital/high-speed design understanding, and experience with multi-processor coherency, DFT-friendly RTL and post-silicon debug.
Verilog, System Verilog, C, C++, Perl, Python, x86, ARM
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CPU Physical Design Engineer
Austin or Mountain View
$138k-$197k/yr OnsiteFull Time
4+ YOEBachelor's degree or equivalent practical experience, 4 years of digital physical design implementation, and experience with synthesis, place and route, timing closure, and signoff tools.
Tcl, Python, Static Timing Analysis (STA), Place and Route (PnR), EMIR
3mo
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Engineering Manager, Digital & Mixed-Signal Hardware
Austin, Texas, United States
OnsiteFull Time
8+ YOE2+ MgmtLead digital and mixed-signal hardware teams; oversee architecture, design reviews, staffing, and process maturity in aerospace/defense; 7-9 years experience; BS or higher in Electrical or Computer Engineering; SI/DFM/DFT expertise; leadership experience.
Altium, Xilinx Vivado, Ansys SiWave, ADS SiPro
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