67 engineer digital design engineering jobs at 53 companies in Vallejo, CA
2d
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Senior Digital Design Engineer
Vancouver or Chandler or San Francisco
$150k-$200k/yr HybridFull Time
6+ YOEBachelor's or master's degree in electrical or computer engineering, 6+ years of digital IC design experience, and hands-on Verilog or SystemVerilog RTL development for complex SoCs or ASICs.
Verilog, SystemVerilog, Synopsys, Cadence, SDC, UPF, CPF
1mo
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AI Silicon, Digital Design Engineer
Palo Alto, California, United States
OnsiteFull Time
8+ YOEB.S. or M.S. in EE/Computer Engineering, 8+ years ASIC/SoC digital design experience, Verilog RTL expertise, EDA tool proficiency, synthesis/timing/LEC experience, and mentorship/communication skills.
Verilog, RTL, EDA tools, Logical Equivalence Checking (LEC), Clock Domain Crossing (CDC), Reset Domain Crossing (RDC)
1w
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Design Engineer III
Menlo Park or Sunnyvale
$140k-$150k/yr HybridFull Time
5+ YOERequires a BS in electrical/computer engineering or computer science, 5+ years of experience, SystemVerilog/UVM verification, coverage and SVA, RTL debug, simulators, Python or Perl, and digital design fundamentals.
SystemVerilog, UVM, VCS, Xcelium, Questa, Verdi, Python, Perl, PrimeTime PX (PTPX), PrimePower, UPF, Palladium, Zebu, RTL-to-GDSII
2mo
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Electrical Design Engineer
Palo Alto, California, United States
$130k-$179k/yr HybridFull Time
7+ YOEBS/MS in Electrical Engineering; 7+ years PCB design experience; strong analog/digital/power circuitry; EMI/SI knowledge; lab test experience; good communication.
PSpice, LTSpice, Hyperlynx, Oscilloscopes, Logic analyzers, PCB design tools, PCB layout constraints
1w
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Hardware Design Engineer
Tempe or San Jose or San Francisco or New York City
$133k-$210k/yr OnsiteFull Time
4+ YOEBachelor's degree or equivalent in electrical or computer engineering, 4+ years in high-speed digital board design and FPGA/RTL development, US citizenship, Secret clearance eligibility, and up to 10% travel.
SystemVerilog, Verilog, VHDL, AMD Vivado, Intel Quartus, Synopsys Synplify, Mentor Xpedition, Cadence, Altium, HyperLynx, Python, TCL, Perl, ModelSim, Questa, Git, Claude Code, Copilot, DDR4, SERDES, UART, I2C, SPI, LVDS, FPGA, RTL, SoC, ADC, DAC, CI/CD, AI
2mo
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Senior Hardware Design Engineer
Newark, California, United States
$130k-$150k/yr OnsiteFull Time
10+ YOEBachelor's in electrical engineering, 10+ years designing high-speed digital/analog circuitry and complex high-density PCBs, 5+ years designing fine-pitch boards, hands-on validation and debugging, proficiency with Python and C, experience with DDR4/DDR5 and PCIe Gen 5/6.
Python, C, DDR4, DDR5, PCIe Gen 5/6, SERDES, Protocol Analyzers, Oscilloscopes, Logic Analyzers, EVT, DVT
3mo
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Senior Rail Track Design Engineer
Coral Gables or New York City or Tampa or San Francisco or Houston or Los Angeles or Chicago or Pensacola or Dallas
HybridFull Time
8+ YOESenior track design engineer with 8+ years rail experience, PE licensure, civil engineering degree; BIM/Digital design tools proficiency; lead complex rail projects in the US.
Bentley OpenRail, OpenRoads, InRoads, MicroStation, Civil 3D
1mo
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Design Verification Engineer
San Francisco, California, United States
OnsiteFull Time
Digital-focused design verification for pre-silicon IP: DV methodology, test-plan and verification environment development, test writing, debug, coverage, and RTL sign-off for tape-out.
2mo
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Mixed Signal Logic Design Engineer
Hillsboro or San Francisco or Phoenix
$142k-$269k/yr OnsiteFull Time
3+ YOEBS or MS with relevant experience in electrical/computer engineering; SystemVerilog; digital and mixed-signal design; multi-clock-domain designs; independent work; team leadership optional.
SystemVerilog, Python, Perl, Bash, CDC analysis, Linting, AMS simulation, Scripting
2mo
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Hardware Design Engineer (Santa Clara, CA, US)
Santa Clara or Palo Alto
$65k-$169k/yr OnsiteFull Time
7+ YOEBachelor's in Electrical/Electronics/Computer Engineering, 7+ years hardware design experience (automotive preferred); analog/digital circuit design; PCB tools (Altium, Cadence, OrCAD); signal/power/thermal management; Ethernet, PCIe, MIPI, GMSL; high-speed validation and debugging.
Altium, Cadence, OrCAD, Ethernet, PCIe, MIPI, GMSL
1w
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Senior IC&E Reactor Protection System Design Engineer
Alameda, California, United States
$141k-$165k/yr OnsiteFull Time
6+ YOEBachelor's degree in electrical or computer engineering, 6 years of relevant engineering experience, regulated or high-reliability environment experience, analog and digital circuit design, schematic capture, PCB design, and lab debugging.
Altium, Cadence, Ki Cad, FPGA, HDL, Verilog
3mo
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Senior RF Design Engineer
San Mateo, California, United States
$170k-$240k/yr OnsiteFull Time
7+ YOE7+ years hands-on wireless RF system development; LTE/cellular integration; PTCRB and carrier certification experience; strong RF, analog/digital skills.
LTE, 5G, RF testing equipment, Network analyzers, Spectrum analyzers, S-parameters, PCB design, EMC/EMI tools, TRP/TIS testing, OTA testing, Ansys HFSS, Keysight ADS
3w
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Principal Electrical Engineer (Design Lead)
San Francisco, California, United States
OnsiteFull Time
Deep experience designing complex high-speed digital and analog/mixed-signal boards, embedded firmware (C/C++), HDL (VHDL/Verilog/SystemVerilog), hardware bring-up, and leading electrical engineering practices for regulated medical devices.
Altium, KiCad, C, C++, Python, VHDL, Verilog, SystemVerilog, HDL, FPGA, MCU, SoC, 10/25/100G Ethernet
1mo
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Manager, Digital Transformation - Design Quality
Fremont, California, United States
$114k-$253k/yr OnsiteFull Time
6+ Mgmt6+ years management experience; bachelor’s degree or equivalent experience; experience in engineering or consulting, quality/process design, digital transformation, change management, and product development quality techniques.
Pareto Analysis, Root Cause Analysis, Statistical Process Control, FMEA
4d
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Senior NVM Digital Designer
Palo Alto, California, United States
$178k-$240k/yr HybridFull Time
3+ YOERequires an MS or PhD in electrical engineering or related field, 3+ years of RTL design experience, and hands-on simulation, verification, Verilog/SystemVerilog, Python, and EDA flow experience.
Python, Verilog-A, SystemVerilog, Verilog, RTL, EDA
2mo
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Sr. Staff Engineer - Digital Assets
San Francisco or Scottsdale or Chicago or New York
$175k-$240k/yr HybridFull Time
12+ YOELead architectural design for cross-border and digital asset payments; 12+ years in distributed systems; Docker; Java/Spring; cloud; SDLC experience.
Docker, Java, Spring, Kubernetes, Maven, Gradle, React, Angular, Kafka, Pub/Sub, AppDynamics
1w
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Manager, Electrical Engineering
San Francisco or San Diego or Alaska or Arkansas or Delaware or Iowa or Mississippi or Missouri or Nebraska or Oklahoma or Rhode Island or South Dakota or Vermont or West Virginia or Wisconsin
$198k-$233k/yr HybridFull Time
8+ YOE8+ MgmtRequires 8+ years managing electrical engineering teams, with embedded systems and low-power design experience, plus expertise in analog and digital circuits, power management, sensor integration, testing, validation, and overseas manufacturing.
1w
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Sr. DSP Systems Engineer (Silicon Engineering)
Palo Alto, California, United States
$175k-$280k/yr OnsiteFull Time
5+ YOEBachelor's degree in a STEM discipline and 5+ years in system-level modeling, digital signal processing, or RF/wireless system design. Proficiency in MATLAB, C/C++, or Python required.
MATLAB, C, C++, Python, GNU Radio, Git, JIRA, Confluence, Bitbucket, Bamboo, ASIC, FPGA, WiFi, LTE, TDMA, CDMA, OFDMA
1mo
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Manager, Digital Transformation - Design Quality
Fremont, California, United States
$114k-$253k/yr OnsiteFull Time
6+ MgmtBachelor's degree or equivalent, 6+ years management experience, experience in engineering/consulting, quality/process improvement, change management, and digital transformation.
QMS, Design for Six Sigma, Failure Mode and Effects Analysis (FMEA), Pareto Analysis, Root Cause Analysis, Statistical Process Control
1mo
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Sr Director, Technical Design & Quality - Old Navy
San Francisco, California, United States
$198k-$267k/yr OnsiteFull Time
15+ YOE15+ years in technical design with expertise in fit, grading, pattern engineering, garment construction, quality assurance, vendor management, and digital tool adoption.
3D, PLM, AI, virtual prototyping
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