226 fpga design engineer jobs at 96 companies in San Jose, CA
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Sr. FPGA Design Engineer
Mountain View or Seattle or Remote
$215k-$300k/yr HybridFull Time
8+ YOEBachelor’s in Electrical/Computer Engineering; 8+ years hardware development; FPGA design, simulation, and synthesis; safety-critical development experience preferred.
2mo
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Sr. FPGA Design Engineer
Milpitas, California, United States
$141k-$240k/yr OnsiteFull Time
3+ YOEExperience designing complex FPGA firmware; proficient with Xilinx/Intel FPGAs; HDL Verilog/SystemVerilog; FPGA tools (Vivado, VCS/Modelsim); timing analysis; knowledge of PCIe, DDR4, 10G, SPI, I2C; collaboration with hardware and software teams.
VCS, Modelsim, Vivado, Verilog, SystemVerilog, PCIe, Aurora, DDR4, 10G, SPI, I2C, embedded Linux
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Senior FPGA Design Engineer
San Jose, California, United States
$150k-$200k/yr OnsiteFull Time
5+ YOEStrong RTL FPGA design experience with Vivado and Protocompiler; FPGA/IP integration; 5+ years; PCIe/USB/Ethernet; BS/MS in EE/EECS/CS; English.
Vivado, Protocompiler, IP Integration, PCIe, USB, Ethernet, SPI
2d
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Senior FPGA Circuit Design Engineer
San Jose, California, United States
$149k-$215k/yr OnsiteFull Time
8+ YOEBachelor’s degree in a relevant technical field and 8+ years of FPGA or ASIC design experience, including microarchitecture, RTL, simulation, verification, timing, power, and cross-functional integration.
FPGA, ASIC, Network-on-Chip (NoC), RTL, Static Timing Analysis (STA)
5d
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ASIC & FPGA Design Engineer Stf - E4
Littleton or Sunnyvale or Denver or Boulder or Louisville or Highlands Ranch or King of Prussia
$136k-$252k/yr OnsiteFull Time
Bachelor of Science in Electrical Engineering or related field, or equivalent experience; ASIC/FPGA design, debugging, or verification experience; active Top Secret clearance and U.S. citizenship required.
ASIC, FPGA, Microsoft Project, Microsoft Office, Atlassian JIRA, Earned Value Management System (EVMS)
2mo
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Sr FPGA Design Engineer
Santa Clara, California, United States
OnsiteFull Time
8+ YOEBSEE or MSEE in EE/CE or related, 8+ years FPGA and embedded hardware development, strong Verilog/SystemVerilog/VHDL skills, experience with AMD/Xilinx/Intel/Altera/Lattice/Microchip platforms, PCB/PCBA and production experience, US work authorization required.
Verilog, SystemVerilog, VHDL, AMD/Xilinx, Intel/Altera, Lattice, Microchip, PCIe, Ethernet, USB, SPI, I2C, UART, CAN, DDR, DSP, Altium, Cadence Allegro, OrCAD, PCB, PCBA, DFM, DFT, EMC, EMI
1w
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Sr. FPGA Design & Verification Engineer
San Francisco or Oakland
$137k-$188k/yr HybridFull Time
2+ YOERequires a master's degree plus 2+ years, bachelor's degree plus 3+ years, or equivalent experience; FPGA/RTL design, VHDL, Verilog, SystemVerilog, simulation, debugging, scripting, and laboratory equipment experience.
VHDL, Verilog, SystemVerilog, Questa, ModelSim, Python, Tcl, MATLAB, shell scripting, oscilloscopes, logic analyzers, FPGA
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Senior FPGA Design Verification Engineer
Sunnyvale, California, United States
$152k-$257k/yr OnsiteFull Time
Advanced knowledge of HVL/UVM and HDL (SystemVerilog, Verilog); experience with coverage-driven verification, constrained-random testing, testbench development, scripting (Perl/Python); experience with emulation/FPGA prototyping, formal methods and ML-assisted verification is a plus.
HVL, UVM, SystemVerilog, Verilog, Perl, Python, FPGA, Emulation, Formal
6d
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Sr. FPGA Design & Verification Engineer
San Francisco, California, United States
$137k-$188k/yr HybridFull Time
2+ YOEMaster's degree plus 2+ years or bachelor's degree plus 3+ years of engineering experience; expertise in FPGA and RTL design, VHDL, Verilog, SystemVerilog, simulation, verification, debugging, laboratory equipment, and scripting.
VHDL, Verilog, SystemVerilog, Questa, ModelSim, Python, Tcl, MATLAB, shell scripting, oscilloscopes, logic analyzers
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Senior FPGA Design Engineer,( Nextest, San Jose, CA)
San Jose, California, United States
$170k-$273k/yr OnsiteFull Time
8+ YOEB.S. or M.S. in Electrical Engineering, 8+ years relevant experience, RTL/Verilog, FPGA transceiver and timing experience, C/C++, EM/FPGA tool flow familiarity, lab equipment experience.
C, C++, Linux, Windows, Verilog HDL, Intel FPGA tool flows, Xilinx FPGA tool flows, UVM, ATE
2mo
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
3mo
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FPGA / VLSI Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
Design and verify RTL/FPGA, perform FPGA prototyping, and system integration for ASIC/SoC platforms; strong SystemVerilog/Verilog; experience with UVM; VHDL is a plus.
SystemVerilog, Verilog, UVM, VHDL, FPGA, SoC
2mo
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Senior FPGA Engineer
Redwood City, California, United States
$150k-$250k/yr OnsiteFull Time
5+ YOEBachelors in ECE or related, 5+ years FPGA design experience, Xilinx tool experience, embedded C/C++, Python, experience with Zynq UltraScale+ MPSoC and Linux embedded systems; U.S. authorization required under ITAR.
Zynq UltraScale+ MPSoC, Xilinx FPGA design tools, C/C++, Python, PetaLinux, Yocto, Linux, Google Meet
3mo
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FPGA Engineer (CA, San Jose)
San Jose, California, United States
HybridFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Experience in FPGA design and verification, proficiency in RTL/C/C++, Python; familiarity with VHDL/Verilog, hardware security, IP core development, and FPGA tools.
C, C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Xilinx, Altera, Versal, Stratix, Avalon, AXI, ACE, IP cores, cocotb, pyuvm
4w
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Senior FPGA Modem Engineer
Mountain View or San Diego
$190k-$280k/yr OnsiteFull Time
10+ YOE10+ years designing and implementing FPGA-based wireless modem solutions; proficiency in HDL, verification, FPGA toolchains, lab debugging, and embedded SW/HW integration.
SystemVerilog, Verilog, VHDL, SystemVerilog/UVM, Cocotb, AMD Vivado, Linux, Git, C, C++, Python
1mo
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FPGA Software
San Carlos, California, United States
$150k-$200k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE,5+ years FPGA/RTL design experience,proficiency in SystemVerilog/Verilog,Vivado/Vitis/Petalinux,ARM SoC platforms,DDR/DMA design,C/C++/Python for bring-up.
SystemVerilog, Verilog, Zynq UltraScale+, Versal, Cyclone 10, Vivado, Vitis, Petalinux, Quartus, Questa, ModelSim, Xcelium, Verilator, UVM, C, C++, Python, TCL, OpenBMC, Redfish, IPMI
2mo
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Sensing & Imaging FPGA Engineer
Cupertino, California, United States
OnsiteFull Time
Develop design solutions and early-stage hardware systems integrating cameras and non-vision sensors for consumer devices; collaborate in cross-functional engineering teams.
2mo
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FPGA Engineer Engineer (eInfochips)
San Jose or Austin
OnsiteFull Time
9+ YOE9+ years experience; proficient in Verilog/System Verilog, EDA tools (VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus), IPXACT, UPF, PCIe/AXI/APB, ARM fabric; scripting with Python/Tcl/Perl; timing signoff and clock-crossing expertise.
Verilog, System Verilog, Python, Tcl, Perl, VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus, IPXACT, UPF
2mo
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SoC Design Engineer
Santa Clara, California, United States
$157k-$160k/yr OnsiteFull Time
1+ YOEMaster's in Electrical or Computer Engineering required, 1+ year digital design experience; RTL/Verilog, SystemVerilog/SVA, Python, Perl; experience with Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator; FPGA prototyping, STA, DFT.
Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator, SystemVerilog, SVA, Python, Perl, Verilog, FPGA
4d
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Hardware Design Engineer
Tempe or San Jose or San Francisco or New York City
$133k-$210k/yr OnsiteFull Time
4+ YOEBachelor's degree or equivalent in electrical or computer engineering, 4+ years in high-speed digital board design and FPGA/RTL development, US citizenship, Secret clearance eligibility, and up to 10% travel.
SystemVerilog, Verilog, VHDL, AMD Vivado, Intel Quartus, Synopsys Synplify, Mentor Xpedition, Cadence, Altium, HyperLynx, Python, TCL, Perl, ModelSim, Questa, Git, Claude Code, Copilot, DDR4, SERDES, UART, I2C, SPI, LVDS, FPGA, RTL, SoC, ADC, DAC, CI/CD, AI
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