292 fpga engineer jobs at 99 companies in Benicia, CA
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FPGA Engineer
Sunnyvale or United States
$150k-$220k/yr HybridFull Time
Bachelor's or master's degree in computer or electrical engineering or equivalent; expertise with SystemVerilog, Xilinx FPGAs, Vivado, RTL, FPGA platforms, interfaces, timing analysis, and debugging.
SystemVerilog, Xilinx, AMD, Vivado, ILA, C, C++, Xilinx Versal, Xilinx Alveo, QSFP+, GTY, GTM, AXI
2mo
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Senior FPGA Engineer, LEO Payload FPGA
Sunnyvale, California, United States
$183k-$248k/yr OnsiteFull Time
7+ YOEBachelor's in Electrical Engineering, 7+ years FPGA/System Verilog experience, proficiency with ASIC/FPGA tools, Python test scripting, Xilinx/AMD/Altera FPGAs, RTL/uArchitecture, timing and power optimization, simulation and validation.
System Verilog, Python, Xilinx, AMD, Altera, uArchitecture, RTL, Cocotb, AXI4, AXI Streaming, SerDes, Interlaken, 50G/100G Ethernet
1w
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Lead FPGA Engineer
Milpitas, California, United States
$118k-$200k/yr OnsiteFull Time
0+ YOEDegree in engineering or related field plus 0–5 years of related experience depending on degree; FPGA RTL, high-speed digital design, SystemVerilog, Verilog, VHDL, firmware integration, debugging, and system testing experience.
FPGA, SystemVerilog, Verilog, VHDL, Xilinx Vivado, Xilinx ISE, Synplify, Questa, ModelSim, Python, MATLAB, OrCAD, PCIe, DDR, 10G SerDes, PCB
1mo
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
4w
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System FPGA Engineer
Santa Clara or Austin
$152k-$228k/yr OnsiteFull Time
5+ YOEBachelor's or higher in engineering/CS and 5+ years FPGA implementation and verification experience; proficiency in Verilog/SystemVerilog, Python, cocotb, git/GitHub, vendor FPGA toolchains; strong communication skills.
Python, git, GitHub, cocotb, Verilog, SystemVerilog, AMD/Xilinx Vivado/Vitis, Intel/Altera Quartus Prime, JTAG, oscilloscope
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Sr. FPGA Verification Engineer
Mountain View, California, United States
$215k-$300k/yr OnsiteFull Time
8+ YOEBachelor’s degree in electrical or computer engineering, 8+ years of electronics hardware development, FPGA digital logic design, industry-standard design, simulation and synthesis tools, and strong problem-solving skills.
FPGA, DO-254
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FPGA Engineer (eInfochips Inc)
Mountain View, California, United States
OnsiteFull Time
Experience with FPGA prototyping, C/C++ test content, SystemVerilog, Python, post-silicon validation, hardware debugging, verification, industry protocols, and cross-functional engineering collaboration.
C, C++, SystemVerilog, HAPS, Xilinx, Python, Perl, Ruby, JTAG, logic analyzers, oscilloscopes, multimeters, AMBA, AXI, AHB, APB, SPI, I2C, I3C, USB
1mo
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Senior FPGA Engineer
Redwood City, California, United States
$150k-$250k/yr OnsiteFull Time
5+ YOEBachelors in ECE or related, 5+ years FPGA design experience, Xilinx tool experience, embedded C/C++, Python, experience with Zynq UltraScale+ MPSoC and Linux embedded systems; U.S. authorization required under ITAR.
Zynq UltraScale+ MPSoC, Xilinx FPGA design tools, C/C++, Python, PetaLinux, Yocto, Linux, Google Meet
1w
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Host and Network IO FPGA Engineer
Sunnyvale or Toronto
HybridFull Time
5+ YOERequires 5+ years producing FPGA solutions, or a master's/PhD in computer or electrical engineering plus 3 years' experience; Verilog, Git, FPGA workflows, TCP/RoCE, and network debugging.
Verilog, Git, Wireshark, TCP, RoCE, Arista, Juniper
3w
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Senior FPGA Modem Engineer
Mountain View or San Diego
$190k-$280k/yr OnsiteFull Time
10+ YOE10+ years designing and implementing FPGA-based wireless modem solutions; proficiency in HDL, verification, FPGA toolchains, lab debugging, and embedded SW/HW integration.
SystemVerilog, Verilog, VHDL, SystemVerilog/UVM, Cocotb, AMD Vivado, Linux, Git, C, C++, Python
3w
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Staff FPGA Engineer (Future Forward)
Sunnyvale, California, United States
$213k-$307k/yr OnsiteFull Time
8+ YOEExpertise in Verilog/SystemVerilog and FPGA design, experience with Vivado/QuestaSim/Chipscope, scripting (Python,Tcl,Perl,Shell), version control (Git,SVN), C/C++, MATLAB, and strong communication skills.
Verilog, SystemVerilog, Vivado, QuestaSim, Chipscope, Python, Tcl, Perl, Shell, Git, SVN, C, C++, MATLAB
12h
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ASIC & FPGA Design Engineer Stf - E4
Littleton or Sunnyvale or Denver or Boulder or Louisville or Highlands Ranch or King of Prussia
$136k-$252k/yr OnsiteFull Time
Bachelor of Science in Electrical Engineering or related field, or equivalent experience; ASIC/FPGA design, debugging, or verification experience; active Top Secret clearance and U.S. citizenship required.
ASIC, FPGA, Microsoft Project, Microsoft Office, Atlassian JIRA, Earned Value Management System (EVMS)
2mo
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Senior FPGA Prototyping Platform Engineer
Santa Clara, California, United States
$168k-$311k/yr OnsiteFull Time
7+ YOEBS in Electrical/Computer Engineering with 7+ years FPGA prototyping or MS with 5+ years; strong FPGA prototyping, lab, and debugging skills.
Synopsys Protocompiler, Xilinx Vivado, ChipScope, Oscilloscopes, Logic Analyzers, Protocol Analyzers
3mo
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FPGA SoC Embedded Engineer (RTOS, Xilinx/Intel)
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
Embedded firmware development for SoC platforms, RTOS-based systems, FPGA/hardware collaboration, C/C++ proficiency, experience with Xilinx/Intel SoC FPGA.
C/C++, RTOS, FPGA, SoC FPGA, Xilinx, Intel (Altera), Verilog, SystemVerilog, UVM, JTAG, Embedded Linux, Zephyr
4w
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FPGA Software
San Carlos, California, United States
$150k-$200k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE,5+ years FPGA/RTL design experience,proficiency in SystemVerilog/Verilog,Vivado/Vitis/Petalinux,ARM SoC platforms,DDR/DMA design,C/C++/Python for bring-up.
SystemVerilog, Verilog, Zynq UltraScale+, Versal, Cyclone 10, Vivado, Vitis, Petalinux, Quartus, Questa, ModelSim, Xcelium, Verilator, UVM, C, C++, Python, TCL, OpenBMC, Redfish, IPMI
2mo
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Sr FPGA Design Engineer
Santa Clara, California, United States
OnsiteFull Time
8+ YOEBSEE or MSEE in EE/CE or related, 8+ years FPGA and embedded hardware development, strong Verilog/SystemVerilog/VHDL skills, experience with AMD/Xilinx/Intel/Altera/Lattice/Microchip platforms, PCB/PCBA and production experience, US work authorization required.
Verilog, SystemVerilog, VHDL, AMD/Xilinx, Intel/Altera, Lattice, Microchip, PCIe, Ethernet, USB, SPI, I2C, UART, CAN, DDR, DSP, Altium, Cadence Allegro, OrCAD, PCB, PCBA, DFM, DFT, EMC, EMI
2mo
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Senior FPGA Prototyping Platform Engineer
Santa Clara, California, United States
$168k-$311k/yr OnsiteFull Time
5+ YOEBS (or equivalent) with 7+ years or MS with 5+ years in FPGA prototyping; expertise in synthesis, place-and-route, timing closure, lab FPGA debug, and coordination with verification and software teams.
Synopsys Protocompiler, Xilinx Vivado, ChipScope, Synopsys HAPS, oscilloscopes, logic analyzers, protocol analyzers
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Sr. FPGA Design & Verification Engineer
San Francisco or Oakland
$137k-$188k/yr HybridFull Time
2+ YOERequires a master's degree plus 2+ years, bachelor's degree plus 3+ years, or equivalent experience; FPGA/RTL design, VHDL, Verilog, SystemVerilog, simulation, debugging, scripting, and laboratory equipment experience.
VHDL, Verilog, SystemVerilog, Questa, ModelSim, Python, Tcl, MATLAB, shell scripting, oscilloscopes, logic analyzers, FPGA
2mo
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ASIC/FPGA Verification Engineer III
Denver or Highlands Ranch or King of Prussia or Sunnyvale
$101k-$178k/yr OnsiteFull Time
3+ YOEB.S. in Electrical Engineering or equivalent, 3+ years professional ASIC/FPGA verification experience, SystemVerilog and UVM/OVM/VMM proficiency, HDL and scripting experience, ability to obtain/maintain DoD Secret clearance (US citizenship required).
SystemVerilog, Universal Verification Methodology (UVM), OVM, VMM, VHDL, Verilog, Linux, Perl, TCL, Python
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Sr. FPGA Design & Verification Engineer
San Francisco, California, United States
$137k-$188k/yr HybridFull Time
2+ YOEMaster's degree plus 2+ years or bachelor's degree plus 3+ years of engineering experience; expertise in FPGA and RTL design, VHDL, Verilog, SystemVerilog, simulation, verification, debugging, laboratory equipment, and scripting.
VHDL, Verilog, SystemVerilog, Questa, ModelSim, Python, Tcl, MATLAB, shell scripting, oscilloscopes, logic analyzers
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