281 rtl engineer jobs at 49 companies in Benicia, CA
1mo
Save
Mark Applied
Hide
RTL Engineer
Mountain View, California, United States
$250k-$375k/yr OnsiteFull Time
5+ YOE5+ years RTL/SoC design to silicon, expert Verilog/SystemVerilog, synthesis/timing/CDC/SDC awareness, microarchitecture skills, collaboration across DV/PD/DFT, and scripting in Python/Tcl.
SystemVerilog, Verilog, Python, Tcl, SDC, STA, UPF, HBM, PCIe, SerDes, RISC-V, FPGA
3w
Save
Mark Applied
Hide
Senior RTL Engineer
Santa Clara, California, United States
$200k-$500k/yr OnsiteFull Time
8+ YOE8+ years RTL design experience for complex digital systems, expert Verilog/SystemVerilog, strong computer architecture and microarchitecture knowledge, tapeout ownership, memory and interconnect familiarity.
Verilog, SystemVerilog, AXI, CHI, ACE, LPDDR, DDR, HBM, FPGA
2mo
Save
Mark Applied
Hide
CPU Systems RTL Engineer
Santa Clara, California, United States
$167k-$251k/yr OnsiteFull Time
5+ YOEMS in Computer/Electrical Engineering with 5+ years CPU RTL experience; strong microarchitecture knowledge; Verilog or VHDL experience; familiarity with timing, power, and simulators; scripting with Perl or Python.
Verilog, VHDL, Perl, Python
1mo
Save
Mark Applied
Hide
Senior RTL Engineer, Interconnect Design
San Francisco, California, United States
$225k-$445k/yr HybridFull Time
Senior RTL engineer with deep Verilog/SystemVerilog expertise, SoC interconnect/NoC experience, protocol knowledge (AXI, APB, CXL, PCIe, Ethernet), RTL signoff flows, and track record from microarchitecture through tape-out.
Verilog, SystemVerilog, AXI, APB, CXL, PCIe, Ethernet, RDMA, RoCE, network-on-chip, NoC, FPGA, lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, design-for-test
1mo
Save
Mark Applied
Hide
RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
1d
Save
Mark Applied
Hide
Senior RTL Design Engineer, TPU
Sunnyvale, California, United States
$163k-$236k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CE/CS or equivalent,8 years ASIC design experience,SystemVerilog/RTL coding,script experience (Tcl, Python, Perl),BLS/CPR? NO (ignore).
SystemVerilog, RTL, Tcl, Python, Perl
2mo
Save
Mark Applied
Hide
Sr. Engineer, RTL Implementation
Austin or Santa Clara
$100k-$500k/yr HybridFull Time
Experienced in high-performance physical design; RTL coding (Verilog/VHDL); synthesis/place-and-run; CPU micro-architecture.
Verilog, VHDL, Synthesis tools, Place and Route tools
2mo
Save
Mark Applied
Hide
Sr. RTL Design Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
$170k-$235k/yr OnsiteFull Time
5+ YOEBachelor’s in electrical/computer engineering or computer science; 5+ years of RTL implementation experience.
Verilog, SystemVerilog, Python, EDA tools, HDL simulators, HDL Lint
1d
Save
Mark Applied
Hide
Senior Staff RTL Design Engineer - CPU Frontend
Santa Clara, California, United States
$206k-$251k/yr OnsiteFull Time
7+ YOEBS/MS in CS/CE/EE or equivalent,7+ years RTL/CPU microarchitecture experience,Proficient in Verilog/SystemVerilog/VHDL,software engineering skills,experience with CPU front-end blocks and verification.
Verilog, SystemVerilog, VHDL, Chisel, FIRRTL, Scala, Bluespec, Git, GitHub, Jira, Confluence, UVM
6d
Save
Mark Applied
Hide
CPU Microarchitect/RTL Engineer - Fetch, Out of Order
Santa Clara, California, United States
OnsiteFull Time
Experienced engineer to drive CPU front-end and out-of-order microarchitecture and RTL development for high-performance, low-power cores.
2w
Save
Mark Applied
Hide
RTL Power Optimization Engineer – New College Grad 2026
Santa Clara, California, United States
$116k-$219k/yr OnsiteFull Time
MS or PhD in EE/CE (pursuing or recent); understanding of RTL low-power design, backend flows, power analysis tools; Python and ML experience; strong communication and RTL debugging skills.
PowerArtist, PrimeTime PX, Python, Verilog
2mo
Save
Mark Applied
Hide
Member of Technical Staff, Hardware, RTL Design Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE and 5+ years industry experience with advanced process nodes (7nm or below); strong RTL, synthesis, physical design, and timing tool experience; expertise in computer architecture and silicon delivery.
System Verilog, VCS, Verdi, Fusion Compiler, PrimeTime, C, C++, python, ISA assembly, PCIe, UCIe, HBM, DDR, AXI, CHI, Static Timing Analysis (STA)
2w
Save
Mark Applied
Hide
RTL Power Optimization Engineer – New College Grad 2026
Santa Clara, California, United States
$116k-$219k/yr OnsiteFull Time
MS or PhD in EE/CE or equivalent; understanding of RTL power optimization, low-power techniques, backend flows, experience with power analysis tools, and strong Python and communication skills.
PowerArtist, PrimeTime PX, Python, Verilog
1mo
Save
Mark Applied
Hide
RTL/Logic Design Engineer
Santa Clara or United States
$166k-$250k/yr HybridFull Time
5+ YOE5+ years digital design experience; expertise in RTL/Verilog, high-speed memory interfaces (HBM, GDDR); familiarity with Synopsys, Cadence, Mentor Graphics; strong simulation, synthesis, timing analysis skills; BS/MS in engineering.
Verilog, Synopsys, Cadence, Mentor Graphics, Register Transfer Level (RTL)
2mo
Save
Mark Applied
Hide
Senior Principal Engineer, Micro-architecture and RTL
Santa Clara, California, United States
$182k-$273k/yr OnsiteFull Time
15+ YOEBachelor's in CS/EE with 15+ yrs; MS with 10-12 yrs; PhD with 8-10 yrs. SystemVerilog RTL, UVM, Ethernet, PCIe, CXL experience; leadership ability.
SystemVerilog, SystemVerilog Assertions, Universal Verification Methodology, RTL, PCIe, CXL, Ethernet
3w
Save
Mark Applied
Hide
Principal PCIe Subsystem RTL lead
San Jose or Santa Clara or Austin or Seattle or Boston
HybridFull Time
10+ YOE10+ years digital IC design experience with 4+ years PCIe subsystem design/integration, strong SystemVerilog RTL skills, experience integrating PCIe controller/SerDes PHY, multi-clock-domain design, and ability to lead architectural work.
SystemVerilog, UVM, PCIe, CXL, SerDes
1mo
Save
Mark Applied
Hide
Micro-Architect and RTL Designer
Mountain View, California, United States
$120k-$600k/yr HybridFull Time
4+ YOE4+ years micro-architecture and RTL design experience; SystemVerilog, Python, C/C++; ASIC/SoC concept-to-silicon experience; synthesis and sign-off flows; verification collaboration; US work authorization and export-control compliance.
SystemVerilog, Python, C/C++
1mo
Save
Mark Applied
Hide
Micro-Architect and RTL Designer
Mountain View, California, United States
$120k-$600k/yr HybridFull Time
4+ YOEConcept-to-silicon ASIC/SoC experience; 4+ years with SystemVerilog, Python, C/C++; production micro-architecture and RTL design experience; synthesis, timing closure, verification collaboration, and high-performance compute or high-speed I/O experience.
SystemVerilog, Python, C/C++
2w
Save
Mark Applied
Hide
Digital IC Design Engineer | BCP
Santa Clara, California, United States
$130k-$241k/yr OnsiteFull Time
3+ YOEB.S. in Electrical Engineering, 3+ years digital design experience; RTL/Verilog/SystemVerilog, Cadence, Python, UVM, and GDSII experience preferred; ability to implement and verify synthesizable RTL to GDSII.
RTL, Verilog/Systemverilog, Cadence, Python, UVM, VAMS, GDSII
1w
Save
Mark Applied
Hide
ASIC Engineer, Design
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's degree or equivalent,6+ years hardware design experience for production silicon,expertise in microarchitecture,RTL and SoC integration,strong communication and collaboration skills.
RTL, Synthesis, Timing Closure, Formal Verification Methodology, SoC, EMR
Explore Jobs