17 fpga engineer jobs at 8 companies in Elk Grove, CA
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Digital Engineer/Principal Digital Engineer
McClellan, California, United States
$101k-$188k/yr OnsiteFull Time
2+ YOESTEM bachelor's degree and 2 or 5 years of related experience depending on level, or qualifying master's/PhD. Requires US citizenship, Secret clearance eligibility, FPGA design with VHDL or Verilog, and EDA tools.
FPGA, VHDL, Verilog, Electronic Design Automation (EDA), Vivado, QuestaSim, AMD/Xilinx 7, Zynq, Kintex, Ultrascale, Versal, DSP, MATLAB
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Staff Engineer Digital
McClellan, California, United States
$198k-$292k/yr OnsiteFull Time
12+ YOEBachelor's with 12 years, master's with 10 years, or PhD with 8 years in STEM; FPGA design with VHDL or Verilog; AMD/Xilinx devices; Vivado, QuestaSim, test benches, and Secret clearance eligibility.
FPGA, VHDL, Verilog, AMD/Xilinx 7, Zynq, Kintex, Ultrascale, Versal, Electronic Design Automation (EDA) Tools, Vivado, QuestaSim, MATLAB, DSP, Software-Defined Radios (SDRs), Ultra-Wideband (UWB)
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Sr Principal Engineer Digital
McClellan, California, United States
$156k-$235k/yr OnsiteFull Time
8+ YOEBachelor's degree in STEM with 8 years of related experience, master's with 6 years, or PhD with 4 years. Requires US citizenship, Secret clearance eligibility, FPGA design with VHDL or Verilog, and EDA tools.
VHDL, Verilog, AMD/Xilinx 7, Zynq, Kintex, Ultrascale, Versal, Electronic Design Automation (EDA) Tools, Vivado, QuestaSim, MATLAB, FPGA, Software-Defined Radios (SDRs)
1mo
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Senior Hardware Design Engineer, Ethernet Switching
Roseville, California, United States
$260k-$470k/yr OnsiteFull Time
10+ YOEBSEE or MSEE; 10+ years hardware engineering experience designing high-speed networking hardware (100G/200G PAM4). Experience with multi-layer high-speed PCBs, signal/power integrity, FPGA/Verilog, and taking products from concept to production.
Verilog, DDR, PCIe, FPGA, VNA, TDR, S-parameters
2mo
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Principal Engineer, Firmware Security
San Jose or Longmont or Folsom
$161k-$318k/yr OnsiteFull Time
10+ YOEBachelor's degree, 10+ years security firmware experience, applied cryptography and post‑quantum expertise, proficiency in C and Python, experience with SoC/FPGA debugging, and knowledge of storage security standards.
C, Python, Rust, JTAG, FPGA, SoC, Caliptra
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Electronics Engineer
McClellan, California, United States
$99k-$153k/yr OnsiteFull Time
1+ YOEBachelor's in engineering (ABET or equivalent) plus 1 year specialized experience with FPGA (VHDL/Verilog), PCB design (Altium/Cadence/OrCad), RF simulation/testing, and use of electronic analysis equipment; transcripts and security clearance required.
VHDL, Verilog, Power Analyzers, Signal Analyzers, Network Analyzers, Oscilloscopes, GPS Simulators, Altium, Cadence, OrCad, Anechoic Chambers, CST Studio, Antenna Magus, ADS Software, Electronic Medical Records (EMR)
3mo
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Senior Electrical Engineer
Irving or Bronx or Sacramento or Dallas
$125k-$135k/yr OnsiteFull Time
10+ YOE10+ years electrical engineering; analog/digital circuit design; up to 600VAC; PCB layout; Ethernet/CAN/RS232; elevator domain knowledge.
Altium, Embedded C, FPGA, CAN, Ethernet, RS232/422
1w
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Principal Engineer - Validation (Systems)
Roseville, California, United States
$75k-$232k/yr OnsiteFull Time
10+ YOE10+ years SoC/silicon validation experience, strong C/C++ and Python scripting, hands-on lab skills with high-speed test equipment, SoC system-level debug, and a BS/MS in Computer/Electrical Engineering or Computer Science.
C, C++, Python, Tcl, oscilloscope, protocol analyzer, logic analyzer, FPGA, VHDL, Verilog, Linux, Windows, PCIe, DDR4, DDR5, SAS, SATA, I2C, SPI, ThreadX, RTOS, MIPS
3mo
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ASIC Senior Verification Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
10+ YOE10+ years in VLSI design/verification; FPGA/EDA; Verilog/SystemVerilog; scripting (Python, TCL, PERL); C/C++; UVM; BS or MS in EE/CS.
Verilog, SystemVerilog, UVM, EDA, C, C++, Python, Perl, TCL
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Sr Engineer I - Validation (Systems)
Burnaby or Roseville
$86k-$186k/yr OnsiteFull Time
5+ YOERequires 5+ years of silicon or SoC validation experience, C/C++ and Python or Tcl, high-speed lab equipment, system-level debugging, and a Computer/Electrical Engineering or Computer Science degree.
C, C++, Python, Tcl, FPGA, VHDL, Verilog, PCIe, DDR4/5, SAS, SATA, I2C, SPI, Linux, Windows, ThreadX, RTOS
1w
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Sr Engineer I - Validation (Systems)
Roseville, California, United States
$70k-$205k/yr OnsiteFull Time
5+ YOE5+ years SoC/silicon validation experience, strong C/C++/Python/Tcl skills, hands-on lab experience with high-speed test equipment, SoC system-level debug, and a Bachelor's in EE/CE/CS.
C, C++, Python, Tcl, Oscilloscope, Protocol Analyzer, Logic Analyzer, FPGA, VHDL, Verilog, Linux, Windows, MIPS, PCIe
2mo
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Senior ASIC verification engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
10+ YOEBachelor's degree in EE/CE, 10+ years VLSI design/verification experience, proficiency in Verilog/SystemVerilog, UVM, scripting (Python, Perl, Tcl), C/C++, strong VLSI architecture and leadership skills.
Python, Perl, Tcl, C, C++, Verilog, SystemVerilog, UVM, Specman, Electronic Design Automation (EDA), FPGA tools
2d
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Technologist, Hardware Development Engineering
Roseville, California, United States
$171k-$227k/yr OnsiteFull Time
Expert hardware engineer with full-lifecycle ownership, board design, ASIC integration, high-speed Ethernet and PCIe, FPGA platforms, SI/PI, DFT, lab debug, and cross-functional technical leadership experience.
FPGA, PCIe, Ethernet, DDR, SerDes, USB, I2C, SPI, MIPI, JTAG, BERT, IBIS/AMI, S-parameters, SPICE, Cadence, Altium, Mentor, Oscilloscopes, Network analyzers, Spectrum analyzers
5d
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HBM Hardware Emulation Architect - SMTS
Folsom or Richardson
$177k-$334k/yr OnsiteFull Time
15+ YOEBachelor's or master's degree in electrical or computer engineering, 15+ years of engineering experience, RTL design and debug, emulation platforms, memory subsystems, SoC architecture, and firmware interaction.
Palladium, Veloce, Zebu, RTL, FPGA
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HBM Hardware Emulation Architect - SMTS
Folsom or Richardson
$177k-$334k/yr OnsiteFull Time
15+ YOEBachelor's or master's degree in electrical or computer engineering or equivalent experience; 15+ years of engineering experience; RTL design, emulation platforms, HBM, SoC architecture, and full-chip debugging experience.
Palladium, Veloce, Zebu, RTL, FPGA
2mo
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HBM Hardware Emulation Architect
Folsom or Richardson
$146k-$309k/yr OnsiteFull Time
10+ YOEBachelor's/Master's in EE/CE or equivalent, 10+ years engineering/design experience, strong RTL design and debug, hands-on hardware emulation platform experience, SoC architecture and firmware interaction expertise.
Palladium, Veloce, Zebu, FPGA
2mo
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HBM Hardware Emulation Architect
Folsom or Richardson
$146k-$309k/yr OnsiteFull Time
10+ YOEBachelor's/Master's in EE/CE or equivalent; 10+ years engineering/design experience; strong RTL design and debug skills; hands-on experience with hardware emulation platforms; SoC architecture and firmware familiarity.
Palladium, Veloce, Zebu, FPGA
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