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Executive IC, Design
Canada or United States
RemoteFull Time
Design leader with track record leading teams and building design systems; experience with AI-powered design tools; cross-disciplinary design across product, brand, and marketing.
Figma AI, Midjourney, AI tooling
1mo
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Head of IC Design
San Jose, California, United States
OnsiteFull Time
15+ YOE15+ years IC design experience with proven global leadership; deep expertise in high-voltage/power IC, mixed-signal integration, semiconductor processes (BCD, HV, GaN preferred); track record delivering silicon on schedule and improving design productivity.
2w
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IC Design Engineer
Berkeley, California, United States
$111k-$223k/yr OnsiteFull Time
2+ YOEDesign and develop high-performance analog/mixed-signal ASICs, perform block design, layout, verification, test and chip integration; collaborate with scientific teams; proficiency with IC design suites and simulators.
Cadence, Spectre, Eldo, HSPICE, FPGA, Verilog, VHDL, PDK
2w
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IC Design Engineer
Berkeley, California, United States
$125k-$182k/yr OnsiteFull Time
2+ YOE2+ years IC design experience (Level 2) or equivalent advanced degree; strong analog/mixed-signal design skills; proficiency with Cadence and transistor-level simulators; ability to design, test, and integrate ASICs for scientific instruments.
Cadence, Spectre, Eldo, HSPICE, Verilog, VHDL, FPGA, PDK
2w
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IC Design Engineer
Chestnut Ridge, New York, United States
$114k-$151k/yr OnsiteFull Time
2+ YOE2+ years BiCMOS IC design with tape-out experience, BS/MS/PhD in Electrical Engineering, RF and wideband design skills, proficiency with Cadence tools and Python, strong collaboration and communication.
Virtuoso, AMS, SpectreRF, Explorer, Assembler, Quantus, EMX, Physical Verification System, Skill, Python, Ansys HFSS
2mo
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IC Design Engineer
San Jose or Irvine
$127k-$203k/yr OnsiteFull Time
10+ YOEBS or MS in Electrical Engineering with 10+ years of IC physical design experience; extensive tool experience (Innovus, VCLP, Formality, LEC, Calibre); Cadence Innovus; TCL scripting; Python.
Innovus, VCLP, Formality, LEC, Calibre, Cadence Innovus, TCL scripting, Python
3mo
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Analog IC Design Engineer
Cupertino or Sunnyvale
OnsiteFull Time
Bachelor's degree in Electrical Engineering; experience in analog IC design preferred.
Verilog, Matlab, C, Oscilloscopes, Spectrum Analyzers, Signal Generators
1d
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Analog IC Design Engineer
Princeton, New Jersey, United States
$82k-$108k/yr OnsiteFull Time
3+ YOERequires degree in electrical/computer/physics engineering, 3+ years analog IC design experience (or master's new grad), US citizenship/permanent residency, knowledge of analog circuits, and Cadence/Spectre tool experience.
Cadence Virtuoso Schematic Editor, Cadence Virtuoso Layout Editor, Spectre, APS SPICE, VerilogA/AMS
3w
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Analog IC Design Engineer
Dallas or Dallas
OnsiteFull Time
1+ YOEBachelor's in EE/ECE or related, 1+ years analog or mixed-signal IC design; strong analog fundamentals; experience with Cadence Spectre or HSPICE; familiarity with CMOS/BiCMOS/BCD; scripting (PERL, Python, SKILL).
Cadence Spectre, HSPICE, PERL, Python, SKILL
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Principal Power IC Design Engineer
Chandler, Arizona, United States
OnsiteFull Time
8+ YOEMSEE (10+ yrs) or PhD (8+ yrs) power IC design experience; transistor-level design of power management circuits; experience with BCD/HV-CMOS, control-loop design; proficiency with Cadence Virtuoso and Spectre/APS; leadership from concept to silicon.
Cadence Virtuoso, Spectre/APS
2w
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Staff IC Design Engineer, Analog (62054)
Lake Oswego, Oregon, United States
OnsiteFull Time
6+ YOE6+ years analog/mixed-signal IC design experience for low-power implantable or portable medical applications; bachelor\u0002s in electrical engineering or related; strong CMOS, transistor-level and layout skills; Cadence tool experience.
Virtuoso XL, Spectre, Xcelium/AMS, Maestro
3mo
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Principal IC Digital Design - SoC Design/Micro-architecture
Santa Clara, California, United States
$159k-$238k/yr OnsiteFull Time
12+ YOESenior digital IC/SoC RTL design with 12+ years experience; expertise in SystemVerilog, micro-architecture, and various interfaces.
Verilog, SystemVerilog, ARM AMBA, PCIe, DDR, LPDDR, I2C, I3C, USB, UART, QSPI/SPI, Perl, Python
4d
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Senior Analog IC Design Engineer
Mounds View, Minnesota, United States
$108k-$162k/yr OnsiteFull Time
4+ YOEBS in electrical/electronic engineering, 4+ years analog/mixed-signal IC design experience (2+ with advanced degree), EMR not relevant; experience with Cadence tools, Spectre/ADE, LabView and Python preferred.
Cadence EDA, Cadence Layout, Spectre, ADE, LabView, Python
4d
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Senior Analog IC Design Engineer
Mounds View, Minnesota, United States
$108k-$162k/yr OnsiteFull Time
4+ YOEBS in Electrical/Electronic Engineering plus 4+ years analog/mixed-signal IC design (or 2+ years with advanced degree). Proficiency with Cadence EDA, Spectre/ADE, mixed-signal verification, lab testing, Python and LabView.
Cadence EDA tools, Spectre, ADE, Cadence Layout tools, LabView, Python
1mo
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PLL IC Design Engineer - TeraWave
San Diego or San Francisco or Renton or Seattle
$230k-$323k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOEB.S. in Electrical Engineering, 7+ years designing fractional-N PLLs/DLLs in advanced FinFET CMOS, proficiency with Spectre, AMS, MATLAB, SystemVerilog, PLL silicon characterization, and ability to work as a U.S. person.
Spectre, AMS, MATLAB, SystemVerilog
2mo
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IC Design Engineer III
Princeton, New Jersey, United States
$92k-$122k/yr OnsiteFull Time
5+ YOEBS EE with 5+ years analog/mixed-signal design; or MS EE with thesis and 2 years; US citizenship or PR; on-site in Princeton, NJ.
Analog circuit design, Op-amps, Comparators, Regulators, HDL Verilog/VHDL, Python, Perl, TCL
1mo
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Junior IC Layout Design Engineer
Richardson, Texas, United States
HybridFull Time
1+ YOE1+ year IC layout and physical verification experience, U.S. person (ITAR) requirement, experience with Cadence Virtuoso/VXL and Assura (DRC/LVS/ERC), BS in Electrical Engineering, exposure to SKILL or Perl a plus.
Cadence Virtuoso, VXL, Assura, DRC, LVS, ERC, SKILL, Perl
1d
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Senior Staff Design Engineer, IC Layout
United States or Seattle
$159k-$238k/yr RemoteFull Time
12+ YOEBachelor's or Master's in computer/electrical engineering,12+ years IC layout experience, expertise in analog/RF/mixed-signal layout, tapeout flows, and mentoring; strong communication and project management.
Cadence Virtuoso, PVS, Siemens Calibre
2mo
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Sr. IC Package Design Engineer (Silicon Engineering)
Austin or Irvine
OnsiteFull Time
5+ YOEBachelor's degree in electrical/computer engineering or physics; 5+ years IC package design experience; strong SI/PI, RF, and CAD tool proficiency.
Cadence APD+/SIP, SIWave, HFSS, ADS, Package design tools
1d
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Distinguished Engineer, Digital IC Design
Santa Clara, California, United States
$210k-$314k/yr OnsiteFull Time
15+ YOEMaster's required (Ph.D. preferred),15+ years experience in uLED/uVCSEL, ASIC architecture, chiplet and multi-die design, demonstrated leadership, patents/publications, system integration expertise.
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