47 ic design engineer jobs at 21 companies in Los Angeles, CA
3mo
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IC Package Design Engineer
Los Angeles or San Francisco or Austin
OnsiteFull Time
Bachelor's degree; IC package physical design experience; Cadence Allegro/Mentor Xpedition; SiP/PoP knowledge; high-speed and SI/PI; DRC/DFM; automation scripting.
Cadence Allegro, Mentor Xpedition, Calibre, CAM350, HFSS, PowerSI
2d
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Analog IC design engineer
Irvine, California, United States
OnsiteFull Time
Requires advanced analog circuit design, simulation, layout, verification, deep-submicron process experience, industrial experience, and a master's or Ph.D. in electrical engineering.
CMOS, SiGe
3mo
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R&D Engineer IC Design
Irvine, California, United States
$108k-$173k/yr OnsiteFull Time
8+ YOEBachelor's + 8+ years or Master's + 6+ years in IC design; physical design flow, PnR, timing closure, verification, scripting.
TCL, Perl, Python, Calibre, Mentor Graphics, GDSII, Netlist
2mo
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Sr. IC Package Design Engineer (Silicon Engineering)
Austin or Irvine
OnsiteFull Time
5+ YOEBachelor's degree in electrical/computer engineering or physics; 5+ years IC package design experience; strong SI/PI, RF, and CAD tool proficiency.
Cadence APD+/SIP, SIWave, HFSS, ADS, Package design tools
1mo
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Principal, IC Digital Design Engineer
Irvine, California, United States
$151k-$223k/yr OnsiteFull Time
12+ YOE12+ years ASIC digital design experience, RTL implementation (SystemVerilog), DSP and high-speed datapath expertise, familiarity with front-end flows (lint, CDC/RDC, synthesis, STA), strong debug and leadership skills.
SystemVerilog, lint, CDC, RDC, synthesis, STA, PNR, emulation, FPGA
1w
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Experienced Analog/Mixed Signal IC Design Engineer
Hillsboro or Newport Beach or Milpitas
$121k-$171k/yr OnsiteFull Time
5+ YOEMSEE and minimum 5 years analog/high-frequency IC design experience in CMOS/BiCMOS; proficiency with EDA tools, EMX/HFSS, ADS/Matlab; lab test and productization experience; strong communication; willingness to travel.
EDA design tools, EMX, HFSS, ADS, Matlab
4d
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PA IC Design (Summer/Fall Co-Op)
Newbury Park, California, United States
$26-$48/hr OnsiteInternship, Temporary
Currently enrolled in an Electrical Engineering MS or PhD program; familiar with power amplifier and RF design, DPD, memory effects, and amplifier modes; willing to work onsite up to six months.
Keysight ADS, Ansys HFSS, Microsoft Word, Microsoft Excel, Microsoft PowerPoint, Microsoft Outlook, network analyzer
1mo
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Principal Design Engineer
Torrance, California, United States
$190k-$230k/yr OnsiteFull Time
7+ YOEMaster's in electrical engineering +10 years or PhD +7 years experience in analog/power IC design; strong device physics knowledge; proficiency with EDA tools and test/characterization; excellent communication and autonomy.
Cadence Specter, Virtuoso XL, Post Parasitic Extraction, Monte Carlo Analysis, EDA
3mo
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Leader of Analog, Mixed-Signal & RF IC Design
Irvine or Carlsbad or San Jose or Valencia or Bengaluru or Munich or Israel or Singapore
$177k-$259k/yr OnsiteFull Time
6+ YOEHands-on analog/mixed-signal/RF IC design experience with IC tape-out, advanced CMOS process familiarity, and proven people-management and cross-functional leadership; BS+11/MS+9/PhD+6 years experience.
CAD
3d
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Senior Principal RFIC Design Engineer
San Jose or Irvine
$171k-$227k/yr OnsiteFull Time
Hands-on RF and analog IC design experience, CMOS technology expertise at 40nm or below, successful design releases and production, EDA tool knowledge, layout experience, and a relevant BS, MS, or PhD.
Cadence, Mentor, Siemens, Ansys, CMOS, RFIC, EDA
1w
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Senior Analog Design Engineer (Teradyne, Agoura Hills, CA))
Agoura Hills, California, United States
$119k-$191k/yr OnsiteFull Time
3+ YOEMSEE with 5 years of experience or PhD in electrical engineering with 3 years of experience designing and characterizing high-frequency mixed-signal ICs; expertise in analog design, CMOS, electromagnetic and transmission line theory required.
Cadence EDA, Cadence Skill, Ocean, Verilog, Verilog-A, PDKs, Automatic Test Equipment (ATE), sampling oscilloscopes, spectrum analyzers, VNAs, signal sources
2mo
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Physical Design Engineer
San Jose or Irvine
$150k-$250k/yr OnsiteFull Time
5+ YOEBachelor's/Master's in EE, 5+ years full-chip physical verification experience, multiple tapeouts, hands-on with ICV or Calibre, ability to assemble PV flow and floorplanning expertise; Tcl/Python/shell automation preferred.
ICV, Calibre, Tcl, Python, Shell
2d
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Analog and Mixed Signal Design Engineer
Pasadena, California, United States
$120k-$160k/yr OnsiteFull Time
2+ YOERequires a B.S. in Electrical Engineering and 2+ years of analog/mixed-signal design experience. Expertise in transistor-level IC design, EDA tools, ADCs, noise analysis, tapeout, and silicon bring-up.
Cadence, Siemens, Synopsys, AI
3mo
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Lead Principal Engineer Analog Mixed-Signal Design
San Jose or El Segundo or California
$190k-$262k/yr HybridFull Time
15+ YOEAdvanced degree (MSEE/PhD), 15+ years analog mixed-signal IC design experience (data converters), team management, ADC architecture and development, AMS IP for production, MATLAB/Simulink and hardware description language experience, strong communication skills.
MATLAB, Simulink, C, System Verilog, Verilog, VHDL
6d
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Principal Engineer-Communication Systems
Irvine or San Diego
$75k-$232k/yr OnsiteFull Time
8+ YOEMaster's or PhD in Electrical Engineering, 8+ years in wireless PHY systems design, signal processing and communication theory, and experience with MATLAB, C/C++, fixed-point simulation, modem design, and IC testing.
MATLAB, C, C++, Wi-Fi, Bluetooth, SoC
1w
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Senior Dam Safety Engineer - FERC IC
Los Angeles, California, United States
$165k-$250k/yr RemoteFull Time
15+ YOELicensed PE with 15+ years consulting experience in FERC Part 12D, dam safety evaluations, and design; MS preferred; PFMA/L2RA and CDSE experience; strong communication and project management.
AutoCAD, GeoStudio, AllPile, Rocscience, HEC-RAS
2mo
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Analog Design Intern - Master's Degree (Quarter Schools / Fall 2026 Start Dates)
Westlake Village, California, United States
$39-$76/hr OnsiteInternship, Full Time
0+ YOEMS or PhD in electrical engineering; experience in analog/mixed-signal IC design; proficiency with EDA tools; experience in high-performance receiver design and layout; knowledge of transistor-level design and device physics.
EDA CAD tools, Analog/Mixed-signal IC design, SiGe BiCMOS, FinFET CMOS
1w
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Software Engineer II
Santa Ana, California, United States
$102k-$145k/yr OnsiteFull Time
2+ YOEDesign and develop data integration and ETL solutions using Informatica/IICS and Azure/BI tools; 2 years related experience and bachelor’s degree in engineering or related field required.
Informatica, IICS, Azure Synopsis, Power BI, DAX, SSIS, SSAS, SSRS, T-SQL, Infor CSD, SAP S4 Hana, SAP Ariba, Blackline, Vistex, UltiPro, Dayforce, Microsoft Dynamics 365, Trimble, Samsara, Tableau, Azure SQL Data Warehouse, Azure Data Lake, Azure Data Factory, Azure Analysis Services, Google’s Big Query, API
2w
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R&D Engineer, Signal Integrity
Calabasas, California, United States
$150k-$250k/yr RemoteFull Time
7+ YOEBS/MS in Electrical Engineering, 7+ years experience in hardware/IC package design or high-frequency modeling, expertise in signal integrity, PCB and substrate technologies, and strong communication skills.
ANSYS HFSS, 3D-Layout, Polar Instruments, Allegro
2mo
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Digital Environment Engineer
El Segundo, California, United States
$170k-$250k/yr OnsiteFull Time
10+ YOEActive Top Secret clearance with SCI eligibility; Master’s degree; 10+ years DoD/IC software acquisition; DevSecOps, hybrid cloud design; SAP/SAR environment experience.
DevSecOps, Hybrid Cloud, SAP/SAR, DoD security
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