36 ic design engineer jobs at 14 companies in Phoenix, AZ
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Principal Power IC Design Engineer
Chandler, Arizona, United States
OnsiteFull Time
Analog DevicesNASDAQ: ADI: Designs and manufactures semiconductors for signal processing and power management.
8+ YOEMSEE (10+ yrs) or PhD (8+ yrs) power IC design experience; transistor-level design of power management circuits; experience with BCD/HV-CMOS, control-loop design; proficiency with Cadence Virtuoso and Spectre/APS; leadership from concept to silicon.
HCLTechNational Stock Exchange of India: HCLTECH: Global provider of information technology services and software consulting.
10+ YOEBachelor's or Master's in Electrical/Electronics Engineering; ~10+ years IC packaging/package design for senior level (4–6+ years mid); hands-on experience with Siemens (Mentor) Xpedition or Cadence Allegro/APD, physical/substrate design, SI/PI-aware design, DFM and design rule compliance.
Cirrus LogicNASDAQ: CRUS: Designs mixed-signal integrated circuits for consumer electronics.
2+ YOEDegree in Electrical or Computer Engineering; 2+ years digital IC design; Verilog RTL; digital design flow; state machines; CMOS VLSI knowledge; strong problem solving.
Amkor TechnologyNasdaq: AMKR: Provides outsourced semiconductor packaging and test services globally.
Bachelor's in engineering required. Experience creating IC package designs and engineering drawings using CAD; strong communication, self-motivation, and ability to work with minimal supervision. Must be a U.S. Person for export-controlled information.
STMicroelectronicsNew York Stock Exchange: STM: Designs and manufactures semiconductor integrated circuits for electronics applications.
10+ YOEBachelor's in Electronic Engineering, 10+ years analog IC design experience, proficiency with Cadence Virtuoso and Mentor Graphics, EM/ESD awareness, bench testing skills, scripting (SKILL/Perl/Python/TCL) a plus, strong communication.
IntelNasdaq: INTC: Designs and manufactures microprocessors and semiconductor components.
0+ YOEDesign and implement physical IC/SoC from RTL to GDS, perform synthesis/place-and-route/CTS/STA, power and noise analysis, verification and optimization using EDA tools.
Senior Control System Integration & Design Engineer
Seattle or Portland or Phoenix or San Francisco
$95k-$155k/yrHybridFull Time
Brown and Caldwell: Provides environmental engineering services for water and infrastructure systems.
5+ YOE5+ years in control system integration/ICS/OT; PLC/SCADA/HMI design and programming; cybersecurity in ICS/OT; PE license preferred; BS in CS/Engineering.
NXP SemiconductorsNASDAQ: NXPI: Designs and manufactures semiconductors for automotive and IoT applications.
3+ YOEMS in Electrical Engineering with 3–5 years IC development experience, or PhD with 1–2 years experience; high-speed analog/mixed-signal design; Cadence tools; MATLAB/Simulink; strong SI/jitter/noise knowledge; English fluency.
Monolithic Power SystemsNasdaq: MPWR: Provides energy-efficient integrated power semiconductor solutions for electronics.
20+ YOEBSEE or MSEE and 20+ years experience in precision analog/mixed-signal IC design, transistor-level and low-power design, ability to translate system requirements, product development experience, and strong communication and leadership skills.
ERMCO: Manufacturer of electrical distribution transformers and power solutions.
8+ YOE3+ MgmtOversee design, development, and manufacturing of three-phase transformers; lead managers and senior ICs; onsite in Waddell, AZ; BS in engineering; 8+ years in transformer design; familiar with IEEE/IEC/DOE standards.
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
12+ YOEMasters in electrical/electronic/mechatronics engineering; 12+ years in power semiconductors/modules; ECAD/MCAD tools; English fluency; senior IC-level individual contributor.
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
6+ YOEMSEE or PhD preferred, 6+ years industry experience, expertise in mixed-signal/analog IC design, Cadence Virtuoso, SPICE simulators, Verilog, Synopsys Liberty, Python; silicon validation and documentation experience.
Sr. Package Layout Engineer, Annapurna Labs - AI Silicon Packaging
Tempe or Austin or Cupertino
$159k-$248k/yrOnsiteFull Time
AmazonNASDAQ: AMZN: Global online retail and cloud computing technology provider.
10+ YOEBachelor's in EE or related, 10+ years IC package layout and physical design experience, expertise with advanced packaging (2.5D/3D, WLP, RDL, TSV), package DRC/DFM, and collaboration with SI/PI and manufacturing teams.