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167 ic design engineer jobs at 63 companies in San Francisco, CA

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IC Package Design Engineer
Los Angeles or San Francisco or Austin
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
Bachelor's degree; IC package physical design experience; Cadence Allegro/Mentor Xpedition; SiP/PoP knowledge; high-speed and SI/PI; DRC/DFM; automation scripting.
Cadence Allegro, Mentor Xpedition, Calibre, CAM350, HFSS, PowerSI
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Physical IC Design Engineer
San Jose, California, United States
OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
8+ YOEIn-depth physical verification experience for advanced nodes, knowledge of DRC/LVS/ERC/PERC, tape-out experience, scripting (Python/Tcl/Perl), and strong communication skills.
StarRC, Quantus, ICV, Calibre, Pegasus, Python, Tcl, Perl, LVS, DRC, ERC, PERC
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Principal Photonics IC Design Engineer
Santa Clara, California, United States
$232k-$368k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
8+ YOEPhD in electrical engineering, physics, applied physics, or related field, or equivalent experience; 8+ years in photonics IC design; Cadence expertise, production tapeout experience, and technical leadership.
Cadence, Virtuoso, SKILL, Ansys Lumerical, ZeMax, MATLAB, Python, Verilog-A, FDTD, FDE, EME
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Principal Photonics IC Design Engineer
Santa Clara, California, United States
$232k-$368k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
8+ YOEPhD in electrical engineering, physics, applied physics, or related field, or equivalent experience; 8+ years in photonics IC design; Cadence expertise, production tapeout experience, photonic device physics, and technical leadership.
Cadence, Virtuoso, PCell, SKILL, Ansys Lumerical, ZeMax, MATLAB, Python, Verilog-A, FDTD, FDE, EME
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Head of IC Design
San Jose, California, United States
OnsiteFull Time
Power Integrations
Power IntegrationsNASDAQ: POWI: Produces high-voltage integrated circuits for efficient power conversion.
15+ YOE15+ years IC design experience with proven global leadership; deep expertise in high-voltage/power IC, mixed-signal integration, semiconductor processes (BCD, HV, GaN preferred); track record delivering silicon on schedule and improving design productivity.
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PLL IC Design Engineer - TeraWave
San Diego or San Francisco or Renton or Seattle
$230k-$323k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOEB.S. in Electrical Engineering, 7+ years designing fractional-N PLLs/DLLs in advanced FinFET CMOS, proficiency with Spectre, AMS, MATLAB, SystemVerilog, PLL silicon characterization, and ability to work as a U.S. person.
Spectre, AMS, MATLAB, SystemVerilog
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Digital IC Design Engineer | BCP
Santa Clara, California, United States
$130k-$241k/yr OnsiteFull Time
Texas Instruments
Texas InstrumentsNASDAQ: TXN: Designs and manufactures semiconductors and integrated circuits.
3+ YOEB.S. in Electrical Engineering, 3+ years digital design experience; RTL/Verilog/SystemVerilog, Cadence, Python, UVM, and GDSII experience preferred; ability to implement and verify synthesizable RTL to GDSII.
RTL, Verilog/Systemverilog, Cadence, Python, UVM, VAMS, GDSII
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Principal Analog IC Design Engineer, High Speed SerDes
San Jose, California, United States
$137k-$254k/yr OnsiteFull Time
Cadence Design Systems
Cadence Design SystemsNASDAQ: CDNS: Develops computational software and hardware for electronic system design.
7+ YOEMinimum 7 years in CMOS SerDes or high-speed I/O IC design; MS or PhD in electrical engineering; analog/mixed-signal design, verification, CAD tools, and circuit simulation experience required.
CAD, Cadence
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5d
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Analog IC Design Engineer, AMS
Boston or Mountain View
$190k-$230k/yr HybridFull Time
Lightmatter
Lightmatter: Develops photonic processors and interconnects for AI data centers
5+ YOEMS with 8+ years or Ph.D. with 5+ years designing analog and mixed-signal circuits; CMOS expertise, Cadence Design Environment experience, lab testing experience, and cross-functional collaboration skills.
Cadence Design Environment, CMOS, MZM
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Analog/RF IC Layout Design Engineer
Colorado Springs or Santa Clara
$120k-$200k/yr OnsiteFull Time
Keysight Technologies
Keysight TechnologiesNYSE: KEYS: Provides electronic design, test, and simulation software and hardware.
7+ YOEBS/MS in Electrical Engineering; 7+ years analog IC layout; 5+ years Cadence Virtuoso Layout XL; DRC/LVS/meter densities; BiCMOS 130 nm+; device matching knowledge; multi-design capability; SVN/Cliosoft/SOS experience; strong teamwork.
Cadence Virtuoso, DRC, LVS, Mentor Calibre, OCEAN, Scripting
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RF/Analog IC Design Engineer
Santa Clara, California, United States
$169k-$253k/yr OnsiteFull Time
Qualcomm
QualcommNASDAQ: QCOM: Designs and manufactures semiconductors and wireless telecommunications products.
3+ YOEBachelor's or advanced degree in Electrical Engineering with 3+ years RF/analog design experience (or equivalent), experience with Cadence/Virtuoso/ADS, transistor-level RFIC design and ASIC experience preferred.
CADENCE, Virtuoso, ADS
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Senior Analog / Mixed-Signal IC Design Engineer
Palo Alto, California, United States
$145k-$165k/yr OnsiteFull Time
PsiQuantum
PsiQuantum: Builds fault-tolerant quantum computers using silicon photonics technology.
Experienced analog/mixed-signal IC design engineer with MS/PhD in EE; CMOS/SiGe, SPICE tools, and lab bring-up experience.
Spectre, HSPICE, Cadence Virtuoso, SystemVerilog RNM, Verilog-A
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Senior Staff Engineer, Digital IC Design
Santa Clara, California, United States
$134k-$201k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
5+ YOEDegree in computer or electrical engineering with 3–5+ years SOC/SoC experience, RTL design in SystemVerilog, SoC integration and timing closure, CDC/clock/reset design, and scripting with Python or Tcl.
SystemVerilog, Python, Tcl
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RF/MS IC Design Engineer, Optical Networking & SERDES
San Jose, California, United States
$112k-$242k/yr OnsiteFull Time
MaxLinear
MaxLinearNASDAQ: MXL: Provides radio-frequency and mixed-signal semiconductor solutions for communications.
3+ YOEBS+5yrs or MS+3yrs or PhD in EE; experience designing RF/mixed-signal ICs for SerDes/optical systems; knowledge of PLLs, VCOs, ADCs/DACs; silicon debug and cross-functional production experience.
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Experienced Analog/Mixed Signal IC Design Engineer
Hillsboro or Newport Beach or Milpitas
$121k-$171k/yr OnsiteFull Time
MACOM
MACOMNASDAQ: MTSI: Designs and manufactures semiconductor products for communications infrastructure.
5+ YOEMSEE and minimum 5 years analog/high-frequency IC design experience in CMOS/BiCMOS; proficiency with EDA tools, EMX/HFSS, ADS/Matlab; lab test and productization experience; strong communication; willingness to travel.
EDA design tools, EMX, HFSS, ADS, Matlab
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Senior Director Analog IC Design
San Jose, California, United States
$294k/yr OnsiteFull Time
Lattice Semiconductor
Lattice SemiconductorNASDAQ: LSCC: Designs and sells low-power programmable logic devices and chips.
Extensive analog/mixed-signal design experience, leadership of engineering teams, expertise in FinFET technologies and transistor-level techniques, hands-on AMS design and post-silicon characterization, BS/MS/PhD in EE.
Cadence, Virtuoso, Spectre
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4w
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IC Package Design Engineer
San Jose, California, United States
$153k-$219k/yr HybridFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
3+ YOEBachelor's (5+ years) or Master’s (3+ years) in Electrical Engineering or related field; experience in package/PCB/high-speed design, power delivery, and EDA tools; scripting (Python, Perl, TCL, shell) and strong collaboration skills.
EDA, Python, Perl, TCL, Shell
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2d
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Senior IC&E Reactor Protection System Design Engineer
Alameda, California, United States
$141k-$165k/yr OnsiteFull Time
Kairos Power
Kairos Power: Developing fluoride salt-cooled nuclear reactors for clean energy.
6+ YOEBachelor's degree in electrical or computer engineering, 6 years of relevant engineering experience, regulated or high-reliability environment experience, analog and digital circuit design, schematic capture, PCB design, and lab debugging.
Altium, Cadence, Ki Cad, FPGA, HDL, Verilog
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2mo
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Analog/RF IC Layout Design Engineer.
Colorado Springs or Santa Clara
$118k-$196k/yr OnsiteFull Time
Keysight Technologies
Keysight TechnologiesNew York Stock Exchange: KEYS: Manufactures hardware and software for electronic test and measurement.
7+ YOEBS/MS in Electrical Engineering or equivalent,7+ years custom analog IC layout experience,5+ years Cadence Virtuoso Layout XL,sub-micron BiCMOS knowledge,device matching,version control experience,US export-control restrictions apply.
Cadence Virtuoso Layout XL, SVN, Cliosoft/SOS, Mentor Calibre, Linux, SKILL, OCEAN
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Physical Design Engineer II (IC)
San Jose, California, United States
$87k-$165k/yr OnsiteFull Time
Arrow Electronics
Arrow ElectronicsNYSE: ARW: Distributes electronic components and enterprise computing solutions globally.
7+ YOEBachelor's in EE/CE/CS or equivalent,7+ years physical design experience (synthesis, PnR, STA), proficiency with Innovus, Tempus, Quantus and TCL, SoC and sub-7nm experience preferred.
Innovus, Tempus, Quantus, TCL, Cadence, Synopsys
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