105 ic design jobs at 33 companies in Texas
3mo
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IC Package Design Engineer
Los Angeles or San Francisco or Austin
OnsiteFull Time
Bachelor's degree; IC package physical design experience; Cadence Allegro/Mentor Xpedition; SiP/PoP knowledge; high-speed and SI/PI; DRC/DFM; automation scripting.
Cadence Allegro, Mentor Xpedition, Calibre, CAM350, HFSS, PowerSI
1mo
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Analog IC Design Engineer
Dallas or Dallas
OnsiteFull Time
1+ YOEBachelor's in EE/ECE or related, 1+ years analog or mixed-signal IC design; strong analog fundamentals; experience with Cadence Spectre or HSPICE; familiarity with CMOS/BiCMOS/BCD; scripting (PERL, Python, SKILL).
Cadence Spectre, HSPICE, PERL, Python, SKILL
1mo
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Junior IC Layout Design Engineer
Richardson, Texas, United States
HybridFull Time
1+ YOE1+ year IC layout and physical verification experience, U.S. person (ITAR) requirement, experience with Cadence Virtuoso/VXL and Assura (DRC/LVS/ERC), BS in Electrical Engineering, exposure to SKILL or Perl a plus.
Cadence Virtuoso, VXL, Assura, DRC, LVS, ERC, SKILL, Perl
2mo
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Sr. IC Package Design Engineer (Silicon Engineering)
Austin or Irvine
OnsiteFull Time
5+ YOEBachelor's degree in electrical/computer engineering or physics; 5+ years IC package design experience; strong SI/PI, RF, and CAD tool proficiency.
Cadence APD+/SIP, SIWave, HFSS, ADS, Package design tools
2mo
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Analog Mixed-Signal IC Design Engineer - TeraWave
San Diego or Renton or California or Texas or Washington
$213k-$299k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
10+ YOEMS/PhD in EE, 10+ years analog/mixed-signal IC design experience in CMOS/SiGe, proficiency with Spectre, AMS, MATLAB, SystemVerilog, silicon characterization, EM/layout expertise, and U.S. work-authorization required.
Spectre, AMS, MATLAB, SystemVerilog
1w
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R&D Engineer IC Design 4
Austin or San Jose
$122k-$195k/yr OnsiteFull Time
6+ YOEDesign and verify RTL/Verilog blocks for ASICs including synthesis, timing closure, formal verification, scripting, and RTL/gate-level power analysis. BS/MS in ECE and 6+ years experience.
Verilog, RTL, TCL, Perl, Synopsys Design Compiler, DC topo, Cadence RTL Compiler, Primetime, liberty (LIB), Synopsys Formality, Cadence Conformal, Spyglass, svn, git
2mo
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Staff Wireless IC Digital Designer
Dallas, Texas, United States
OnsiteFull Time
8+ YOESenior level design engineer with 8-12 years in digital RF/wireless design, IC/SoC development, RTL, and verification.
RTL, Synthesis, STA, ATPG, RFIC, SoC, Digital design, FPGA design
8h
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3D-IC Application Engineer
Austin or Boulder or Fremont or San Diego or Santa Clara or Wilsonville
$125k-$251k/yr HybridFull Time
4+ YOEMSEE/BSEE and 4+ years of design experience, advanced IC package or interposer layout expertise, package design tools, scripting, Windows/Linux, and customer-facing applications engineering skills.
Innovator 3D IC Layout, Innovator3D IC Integrator, Xpedition, Calibre, HyperLynx, Cadence APD/SiP, Siemens Xpedition/i3DL, Siemens XSI/i3DI, Cadence OrbitIO/ISP, Synopsys 3DIC Compiler, Microsoft Excel, TSMC InFO, CoWoS, Intel EMIB, Foveros, ASE FoCUS, Amkor SWIFT, Samsung I/H/X-Cube, Verilog, LEF/DEF, GDS, OASIS, Sigrity, SIWave, ADS, Siemens Calibre DRC, Siemens Calibre LVS, 3DSTACK, Microsoft Word, Microsoft PowerPoint, VBS, Python, Tcl, Perl, Windows, Linux
1mo
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Design Director
Dallas, Texas, United States
OnsiteFull Time
10+ YOE5+ MgmtLead analog/mixed-signal power IC design from concept to release; 10+ years analog/power IC experience, proven design management, transistor-level design, layout oversight, silicon validation, and strong communication skills.
Cadence, SPICE, LVS, DRC
2mo
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Mixed Signal IC Layout Designer (RS-50022405)
Austin, Texas, United States
OnsiteFull Time
10+ YOEAssociates Degree in Electronic/IC layout CAD; 10+ years IC layout; analog/mixed-signal layouts; Cadence Virtuoso XL; Mentor Calibre; floor planning.
Cadence Virtuoso XL, Mentor Calibre, layout CAD tools, foundry PDKs
2mo
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Analog Design Engineer
Austin, Texas, United States
$317k/yr OnsiteFull Time
10+ YOE10+ years analog/mixed-signal IC design; MS or PhD in Electrical Engineering; 25 Gbps SerDes experience; Cadence tools; post-silicon bring-up; collaborative team player.
Cadence Virtuoso, Cadence Spectre, Verilog-A, EM-IR, Monte Carlo, Post-silicon test equipment
3w
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Principal Engineer, Analog Design
Richardson, Texas, United States
$153k-$265k/yr OnsiteFull Time
10+ YOEBachelor’s degree in electrical engineering,10+ years analog/mixed-signal IC design experience, transistor-level design and simulation, familiarity with Cadence Virtuoso/Spectre, strong analytical and debugging skills.
Cadence Virtuoso, Spectre, Python, MATLAB
2mo
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CPU Physical Design Engineer
Austin, Texas, United States
$106k-$173k/yr OnsiteFull Time
2+ YOEBS in CE/EE with 2+ years or MS with 1+ years; 1+ year in synthesis; IC design tools; DRC/LVS; TCL scripting.
Synopsys, Cadence, Synthesis tools, Place and Route, Static Timing Analysis, DRC/LVS, TCL Scripting
3w
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Principal Engineer, Analog Design
Richardson, Texas, United States
$153k-$265k/yr OnsiteFull Time
10+ YOE10+ years analog/mixed-signal IC design experience, degree in electrical engineering, transistor-level CMOS design and simulation, Cadence Virtuoso/Spectre experience, Python or MATLAB scripting, strong analytical and communication skills.
Cadence Virtuoso, Spectre, Python, MATLAB
2mo
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Senior Analog Design Engineer
Austin, Texas, United States
$125k-$231k/yr HybridFull Time
3+ YOEMS in Electrical Engineering or equivalent with 3+ years analog/mixed-signal IC design; strong CAD, UNIX, MATLAB skills; good communication and leadership potential.
UNIX, MATLAB, Cadence (CAD tools), Verilog, VerilogA, Scripting (Tcl, Perl, SKILL)
5h
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3D-IC Application Engineer
Austin or Boulder or Fremont or San Diego or Santa Clara or Wilsonville
$125k-$251k/yr HybridFull Time
4+ YOEMSEE/BSEE and 4+ years of design experience with advanced IC package or interposer layout. Requires package design tools, scripting, Windows/Linux, and strong presentation and customer skills.
Innovator 3D IC Layout, Innovator3D IC Integrator, Xpedition, Calibre, HyperLynx, Cadence APD/SiP, Siemens XSI/i3DI, Cadence OrbitIO/ISP, Synopsys 3DIC Compiler, Microsoft Excel, TSMC InFO, CoWoS, Intel EMIB, Foveros, ASE FoCUS, Amkor SWIFT, Samsung I/H/X-Cube, Verilog, LEF/DEF, GDS, OASIS, Sigrity, SIWave, ADS, Microsoft Word, Microsoft PowerPoint, VBS, Python, Tcl, Perl, Windows, Linux
2mo
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Analog Design Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years designing advanced analog/mixed-signal ICs (PLLs, ADCs/DACs, SerDes, timing circuits) with FinFET/GAA process experience; B.Sc/M.Sc in EE/CE; tape-out, layout understanding, verification, and teamwork skills.
4d
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Senior Principal RF Design Engineer
Austin or Burlington or Cary
OnsiteFull Time
10+ YOEExpertise in mmWave RF IC design (30+ GHz), PA/LNA/mixer/VCO and PLL design, EM and thermal modeling, lab validation experience; usually M.Sc./Ph.D.; 10+ years industry experience.
VSS, Cadence Virtuoso, VRF, EMX, Clarity, Layout MXL, QRC, Pegasus, spectrum analyzer, VNA, probe station
1w
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Principal Analog Design Engineer
Plano, Texas, United States
HybridFull Time
10+ YOE10+ years experience in power management/PMIC analog and mixed-signal IC design; degree in electronics engineering; strong CMOS power management knowledge; technical leadership and communication skills; ability to travel occasionally.
2w
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Principal Analog Design Engineer
Richardson or San Jose
$170k-$222k/yr HybridFull Time
12+ YOEBachelor's in Electrical Engineering,12+ years semiconductor experience,8+ years analog/mixed-signal IC design with DC-DC converter expertise,EMIR/EDA tool experience,ability to communicate technical concepts.
EMIR, Cadence Virtuoso, Simplis, ADS
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