2mo
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Mechanical Layout Engineer
Woburn, Massachusetts, United States
$70k-$80k/yr OnsiteFull Time
3+ YOE3+ years in mechanical layout/CAD; SolidWorks; create layouts and shop drawings; BOM support; collaborate with sales/engineering.
SolidWorks, AutoCAD, Revit, PDM, CAD automation tools
1mo
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Layout Engineer, DEG
Boise, Idaho, United States
OnsiteFull Time
Experience performing physical layout with Cadence Virtuoso, familiarity with DRC/LVS and physical verification, ability to plan/document/review layout goals with cross-site teams.
Cadence Virtuoso, DRC, LVS
6d
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Layout Engineer - Labs
San Francisco, California, United States
$212k-$312k/yr OnsiteFull Time
8+ YOE8+ years PCB layout experience, expert Altium Designer skills, strong signal/power integrity and mixed-signal layout knowledge, DFM/IPC familiarity, and cross-functional collaboration on flight-grade hardware.
Altium Designer, SolidWorks, Creo, Gerber, ODB++
3mo
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US Expansion Layout Engineer
Boise, Idaho, United States
OnsiteFull Time
2+ YOEBachelor's or Master's in Engineering; 2+ years in layout planning; AutoCAD; Revit; Navisworks; BIM 360; data analysis and visualization (SQL, Python, Tableau, PowerBI); semiconductor environment preferred.
AutoCAD, Revit, Navisworks, BIM 360, SQL, Python, Tableau, PowerBI
1mo
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Analog Layout Engineer
Austin, Texas, United States
OnsiteFull Time
Design and implement analog/mixed-signal layout for SerDes, PLLs, and sensors; translate circuit designs into silicon; collaborate with circuit designers and multidisciplinary teams; use advanced layout tools.
1mo
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RET Layout/Mask Engineer
Dallas, Texas, United States
OnsiteFull Time
5+ YOEBachelors in EE/Physics/CS/Chem, 5+ years layout/mask design, proficiency with Cadence and Synopsys EDA tools, scripting (Python, SKILL, Perl), experience with PG flows/OPC and strong lithography knowledge.
Cadence, Synopsys, Python, SKILL, Perl
2mo
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Layout Engineer
Stuart, Florida, United States
OnsiteFull Time
Experience with Zeiss Inspect/GOM Inspect; optical/structured light scanning (ATOS); GD&T; read drawings; MS Office; Python or VB scripting optional; familiarity with ISO9001/17025/AS9100/NADCAP; US person status.
Zeiss Inspect, GOM Inspect, ATOS, Optical Scanning, Python, Visual Basic, Microsoft Office
1mo
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Staff Analog Layout Engineer
San Jose or Hsinchu
OnsiteFull Time
3+ YOESenior/Staff level IC layout engineer with 3-8+ years in deep-submicron analog/RF layouts; strong EDA/tool experience and EM/IR knowledge.
Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre, Siemens ICV
2mo
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IC Layout engineer
Irvine, California, United States
$86k-$138k/yr OnsiteFull Time
1+ YOEProficient in Virtuoso and Calibre, experience validating LVS/DRC/ERC/ANT/ESD, layout experience in high-speed/mixed-signal circuits, knowledge of N7/N5/N3 processes, Bachelor's degree required.
Virtuoso, Calibre, Cadence
2w
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PCB Layout Engineer
San Carlos, California, United States
$128k-$160k/yr OnsiteFull Time
1+ YOEBachelor's in EE/CompE/Physics or related, 1+ years PCB layout experience for multilayer/high-speed designs, familiarity with signal/power/thermal/EMI considerations, and experience with PCB design tools and manufacturability.
Altium Designer, Cadence Allegro, Mentor Graphics
1mo
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PCB Layout Engineer
Irving, Texas, United States
$55k-$111k/yr OnsiteFull Time
0.5+ YOEMinimum six months relevant design/manufacturing experience (medical device experience preferred); ability to design complex PCB layouts, create footprints, maintain eCAD libraries, collaborate across teams, and communicate effectively.
Cadence Concept HDL, Allegro, Altium Designer, Microsoft Office, Siemens Teamcenter
2w
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PCB Layout Engineer
Sunnyvale, California, United States
$144k-$204k/yr OnsiteFull Time
6+ YOE6+ years PCB layout experience for high-speed, HDI, and rigid‑flex designs; experience with DDR/PCIe/USB/MIPI interfaces; collaboration with electrical/mechanical teams; proficiency with Cadence Allegro or Mentor Xpedition.
Cadence Allegro, Mentor Xpedition, HyperLynx, Sigrity
1mo
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Senior PCB Layout Engineer
Sunnyvale, California, United States
$106k-$214k/yr OnsiteFull Time
8+ YOE8+ years PCB layout experience, expert in Cadence Allegro, high-speed design, SI/PI and impedance control, HDI and manufacturing knowledge, ability to lead layout planning and mentor junior designers.
Cadence Allegro PCB Designer, Cadence Allegro, Constraint Manager, SKILL, ODB++, IPC-2581, Gerber
1mo
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Layout Support Engineer
Andover, Massachusetts, United States
$69k-$131k/yr OnsiteFull Time
2+ YOEU.S. citizenship and ability to obtain/maintain DoD Secret clearance; typically a university degree plus ≥2 years IC layout and physical verification experience; familiarity with Cadence Virtuoso, DRC/LVS, photomask/reticle flows, scripting (Skill/Python), and Linux.
Cadence Virtuoso, DRC, LVS, Skill, Python, Linux, Microsoft Office
1mo
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PCB Layout Engineer
Irving, Texas, United States
$55k-$111k/yr OnsiteFull Time
0.5+ YOEMinimum six months design/manufacturing experience (medical devices), PCB layout and documentation, strong communication and organizational skills, ability to work in matrixed teams, ~5% travel. Preferred experience with Cadence/Allegro or Altium, IPC standards, PLM and Microsoft Office.
Cadence Concept HDL, Allegro, Altium Designer, Microsoft Office, Siemens Team Center
1mo
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Senior PCB Layout Engineer
New Providence, New Jersey, United States
$120k-$192k/yr OnsiteFull Time
7+ YOEBachelor's in Electrical Engineering, 7+ years PCB layout experience for high-speed/high-density designs, proficiency with Allegro PCB Design, DeHDL, Allegro APD, knowledge of PCB fabrication and DFM, and SI/PI/thermal practices.
Allegro PCB Design, DeHDL, Allegro APD
1mo
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Senior Package Layout Engineer - Hardware
Santa Clara or Nevada or Washington or Arizona or Oregon or California
$136k-$259k/yr HybridFull Time
5+ YOEB.S. in Electrical Engineering (or equivalent), 5+ years PCB/layout experience (graphics cards, motherboards, HDI preferred), substrate layout experience, Cadence APD/SiP and Constraint Manager experience, high-speed signal integrity knowledge; Virtuoso/Calibre/Valor a plus.
Cadence APD, SiP, Constraint Manager, Virtuoso, Calibre, Valor
1mo
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Senior Substrate Layout Engineer
Phoenix or Andover
OnsiteFull Time
4+ YOEBachelor's in electrical/electronics engineering, 4+ years HDI package/layout experience, proficiency with Cadence APD+ and Constraint Manager, CAM350/Blueprint, knowledge of HDI/flip‑chip/interposer designs and JEDEC/IPC standards; must have or obtain U.S. government security clearance.
Cadence APD+, Cadence Constraint Manager, CAM350, Blueprint, Ansys, Sigrity, Clarity
2mo
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Analog IC Layout Engineer
Fremont, California, United States
$83k-$139k/yr OnsiteFull Time
2+ YOE2+ years analog/mixed-signal IC layout; 1+ year FinFET; problem-solving ability; strong layout skills.
Analog layout, Mixed-signal layout, SKILL, TCL, Shell, C/C++, Python
2mo
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IC Layout Design Engineer
Richardson, Texas, United States
HybridFull Time
3+ YOE3-5 years in RF/Analog/Mixed Signal layout; Cadence Virtuoso/VXL; Calibre; BD/verification; BS in Electrical Engineering; hybrid work arrangement.
Cadence Virtuoso, Cadence VXL, Calibre, PERL, SKILL, PDV
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