135 layout engineer jobs at 52 companies in Hollister, CA
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Staff Analog Layout Engineer
San Jose or Hsinchu
OnsiteFull Time
3+ YOESenior/Staff level IC layout engineer with 3-8+ years in deep-submicron analog/RF layouts; strong EDA/tool experience and EM/IR knowledge.
Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre, Siemens ICV
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Senior PCB Layout Engineer
Sunnyvale, California, United States
$106k-$214k/yr OnsiteFull Time
8+ YOE8+ years PCB layout experience, expert in Cadence Allegro, high-speed design, SI/PI and impedance control, HDI and manufacturing knowledge, ability to lead layout planning and mentor junior designers.
Cadence Allegro PCB Designer, Cadence Allegro, Constraint Manager, SKILL, ODB++, IPC-2581, Gerber
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Senior Package Layout Engineer - Hardware
Santa Clara or Nevada or Washington or Arizona or Oregon or California
$136k-$259k/yr HybridFull Time
5+ YOEB.S. in Electrical Engineering (or equivalent), 5+ years PCB/layout experience (graphics cards, motherboards, HDI preferred), substrate layout experience, Cadence APD/SiP and Constraint Manager experience, high-speed signal integrity knowledge; Virtuoso/Calibre/Valor a plus.
Cadence APD, SiP, Constraint Manager, Virtuoso, Calibre, Valor
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Senior PCB Layout Engineer
Sunnyvale, California, United States
$106k-$214k/yr OnsiteFull Time
8+ YOE8+ years PCB layout experience; expert in Cadence Allegro and Constraint Manager; strong high-speed design, SI/PI, HDI, impedance control, and PCB manufacturing knowledge.
Cadence Design Systems, Cadence Allegro PCB Designer, Cadence Allegro, Constraint Manager, SKILL, ODB++, IPC-2581, Gerber
1mo
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Senior PCB Layout Engineer
Sunnyvale, California, United States
$106k-$214k/yr OnsiteFull Time
8+ YOE8+ years PCB layout experience with expert Cadence Allegro proficiency, high-speed design, impedance/stackup planning, HDI, EMI/EMC, PCB fabrication knowledge, and mentoring experience.
Cadence Design Systems, Allegro PCB Designer, Cadence Allegro, Constraint Manager, SKILL, ODB++, IPC-2581, Gerber
3w
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Layout Design Engineer (SRAM)
Santa Clara, California, United States
$45k-$121k/yr OnsiteFull Time
10+ YOEBSEE or equivalent, 10+ years custom IC layout experience with 5+ years in SRAM/memory IP, advanced-node (FinFET/GAA) experience, Cadence Virtuoso and Calibre/ICV proficiency, DRC/LVS debugging, mentoring ability.
Cadence Virtuoso, Calibre, ICV
6d
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Staff Engineer, PCB Layout
San Jose, California, United States
$150k-$240k/yr OnsiteFull Time
7+ YOE7+ years PCB layout experience with Cadence Allegro (16.x/17.x), high-density and high-speed designs, knowledge of PCB/PCBA manufacturing, IPC standards, signal integrity, EMC/EMI; bachelor's degree or equivalent.
Cadence Allegro, Valor Trilogy 5000
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Senior / Principal Layout Engineer – Module Architecture (Pathfinding)
San Jose, California, United States
$202k-$344k/yr OnsiteFull Time
8+ YOEBachelor's in Electrical Engineering,8+ years high-speed PCB layout experience, expertise in DDR/LPDDR, SI/PI and PDN, proficiency with Cadence Allegro/OrCAD and AI tools, ability to influence architecture decisions.
Cadence Allegro, OrCAD, AI tools
2mo
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Senior Photonic Layout Design Engineer
Santa Clara, California, United States
$132k-$236k/yr OnsiteFull Time
6+ YOEBS/MS/PhD in Electrical Engineering or Physics; 6+ years full-chip layout experience; Cadence Virtuoso; silicon photonics; layout automation scripting; DRC/LVS proficiency.
Cadence Virtuoso, Calibre, ICV, Dracula, PrimeYield, Python, SKILL, Perl, TCL, C++
1w
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Senior / Principal Layout Engineer – Module Architecture (Pathfinding)
San Jose, California, United States
$202k-$344k/yr OnsiteFull Time
8+ YOE8+ years high-speed PCB/layout experience, expertise in DDR/LPDDR interfaces, SI/PI and PDN, proficiency with Cadence Allegro/OrCAD, and experience influencing architecture decisions in pathfinding environments.
Cadence Allegro, OrCAD, AI tools
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Staff PCB Layout Design Engineer
Mountain View or Sunnyvale
$218k-$245k/yr HybridFull Time
10+ YOEBachelor's in engineering required; 10 years experience in PCB layout and related roles; 8 years with design tools including Mentor Graphics; experience with HDI, high-power boards, high-speed buses, DFM/DFT, and leading design/supplier teams.
Mentor Graphics, ECAD
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Staff Custom Analog Layout Engineer
San Jose or United States
$139k-$259k/yr HybridFull Time
10+ YOEBS degree or equivalent; 10+ years in analog/mixed-signal layout design; proficient with layout tools and DRC/LVS/ERC flows.
Virtuoso, Laker, Calibre, PVS, IC Validator, DRC/LVS/ERC tools, RC extraction, EM/IR analysis
1w
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Layout (FIRE) Extraction Engineer
Milpitas, California, United States
$120k-$160k/yr OnsiteFull Time
Bachelor's in electrical engineering or related, experience with OPC/RET and mask/CMOS processes, scripting (Python/Perl/Tcl/Shell), Linux, and collaboration with design/lithography/fab teams.
Mentor Graphics Calibre OPC/ILT, Synopsys Sentaurus/Litho, ASML Brion Tachyon, Cadence, Synopsys, KLayout, Linux, Python, Perl, Tcl, Shell
2mo
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Analog/RF IC Layout Design Engineer
Colorado Springs or Santa Clara
$120k-$200k/yr OnsiteFull Time
7+ YOEBS/MS in Electrical Engineering; 7+ years analog IC layout; 5+ years Cadence Virtuoso Layout XL; DRC/LVS/meter densities; BiCMOS 130 nm+; device matching knowledge; multi-design capability; SVN/Cliosoft/SOS experience; strong teamwork.
Cadence Virtuoso, DRC, LVS, Mentor Calibre, OCEAN, Scripting
1mo
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Digital Layout Design Engineer
Santa Clara, California, United States
OnsiteFull Time
Design custom digital macros and libraries for ASICs at advanced technology nodes; collaborate with integration, CAD, circuit, and technology engineering teams.
1mo
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Sr. Package Layout Engineer, Annapurna Labs - AI Silicon Packaging
Tempe or Austin or Cupertino
$159k-$248k/yr OnsiteFull Time
10+ YOEBachelor's in EE or related, 10+ years IC package layout and physical design experience, expertise with advanced packaging (2.5D/3D, WLP, RDL, TSV), package DRC/DFM, and collaboration with SI/PI and manufacturing teams.
Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, Python, TCL, Skill, Ravel
1mo
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Principal/Senior High-Speed Analog Layout Engineer
Irvine or San Jose or Ottawa
OnsiteFull Time
10+ YOE10+ years analog/mixed-signal layout experience in advanced CMOS/FinFET (TSMC preferred), expertise with Cadence Virtuoso, Calibre, Pegasus, LVS/DRC/PERC/ERC flows, and leadership/mentoring experience; scripting with SKILL/TCL/Python a plus.
Cadence Virtuoso, Calibre, Pegasus, SKILL, TCL, Python
2mo
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Analog/RF IC Layout Design Engineer.
Colorado Springs or Santa Clara
$118k-$196k/yr OnsiteFull Time
7+ YOEBS/MS in Electrical Engineering or equivalent,7+ years custom analog IC layout experience,5+ years Cadence Virtuoso Layout XL,sub-micron BiCMOS knowledge,device matching,version control experience,US export-control restrictions apply.
Cadence Virtuoso Layout XL, SVN, Cliosoft/SOS, Mentor Calibre, Linux, SKILL, OCEAN
1w
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IC Package Layout Team Leader
San Jose, California, United States
$211k-$305k/yr HybridFull Time
5+ YOEDegree in electrical engineering with relevant experience, 5+ years package/layout experience, high-speed routing and PDN knowledge, EDA tool proficiency, and leadership/mentorship experience.
Cadence APD+, Python, Perl, TCL
1w
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Sr. Staff Engineer, Analog/Mixed-Signal Design
San Jose, California, United States
$180k-$223k/yr OnsiteFull Time
6+ YOEM.S. in Electrical Engineering,6+ years analog/mixed-signal design,experience with high-speed analog blocks and FinFET CMOS,proficient with Cadence/ADE/Layout/Spectre;Python and SKILL preferred.
Cadence, ADE, Layout, Spectre, Python, SKILL