HiringCafe
Join our community

21 noc engineer jobs at 12 companies in Tracy, CA

2mo
Save
Mark Applied
Hide
SR ASIC Design Engineer - NoC & AXI Interconnect
Santa Clara, California, United States
$175k-$300k/yr OnsiteFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
Experience in NoC design, AXI/ACE/APB interfaces, queuing, collaboration with architecture/IP/PD teams; Bachelors or Masters in computer or electrical engineering; Santa Clara, CA location; not eligible for visa sponsorship
SystemVerilog, Verilog, VCS, Perl, Python, Shell, NoC, AXI, ACE, APB, Queuing
Job PostingView all
6d
Save
Mark Applied
Hide
Principal NoC IP Micro-Architect
San Jose, California, United States
$210k-$299k/yr OnsiteFull Time
Altera
Altera: Manufacturer of field-programmable gate arrays and programmable logic devices.
15+ YOE15+ years in NoC IP and RTL design with SystemVerilog, strong RTL validation and SoC interconnect architecture experience; proficiency in C/C++/Perl/Python/TCL/Unix Shell; bachelor’s or master’s in EE/CE.
System Verilog, VCS, Synopsys, C, C++, Perl, Python, TCL, Unix Shell
Job PostingView all
1mo
Save
Mark Applied
Hide
Design Verification Engineer
San Jose, California, United States
$96k-$176k/yr OnsiteFull Time
Arrow Electronics
Arrow ElectronicsNYSE: ARW: Distributes electronic components and enterprise computing solutions globally.
5+ YOEExpertise in SV/UVM, AXI/NOC/Ethernet/PCIe/UCIe, ARM/RISC-V with C, regression and coverage closure; typically requires 5+ years' related experience and a 4-year degree (or equivalent).
SV, UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, NVMe, NAND, DDR
Job PostingView all
2mo
Save
Mark Applied
Hide
Lead RTL Design Engineer
Austin or Pittsburgh or San Jose
$160k-$250k/yr OnsiteFull Time
Efficient Computer
Efficient Computer: Developing ultra-low-power general-purpose processors for edge AI computing.
8+ YOE8+ years RTL design with tape-out ownership; SystemVerilog; on-chip networks, memory subsystems, NoC; low-power design; DV collaboration; silicon bring-up.
SystemVerilog, UPF, AXI, AHB, APB, TileLink, NoC, SDC, STA, ATPG, DFT, memory compiler
Job PostingView all
3w
Save
Mark Applied
Hide
Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
OnsiteFull Time
SiFive
SiFive: Designs and licenses high-performance RISC-V processor intellectual property.
Staff-level hardware engineer with experience designing interconnects, cache/coherency, RTL generators using Chisel/Scala; proficiency in Verilog/System Verilog/VHDL and hardware-software engineering practices; BS/MS in EE/CE/CS or equivalent.
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, TileLink, RISC-V, NoC, AXI, AHB, APB, CHI, Bluespec, Git, GitHub, Jira, Confluence
Job PostingView all
3mo
Save
Mark Applied
Hide
Sr. Staff ASIC Verification Engineer
Palo Alto, California, United States
$237k-$296k/yr OnsiteFull Time
Rivian
RivianNASDAQ: RIVN: Designs and manufactures electric vehicles and charging networks.
10+ YOETypically 10+ years in ASIC design verification; BS/MS or PhD in Electrical or Computer Engineering; deep computer architecture; NoC; UPF/CPF; Systolic Arrays/NPUs; CNN/Transformer mapping; compilers/toolchains.
SystemVerilog, UVM, SVA, ISO 26262, FIA, Emulation, FPGA
Job PostingView all
1w
Save
Mark Applied
Hide
Custom SOC IP Verification Engineer
Santa Clara or Austin
$168k-$311k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
6+ YOE6+ years ASIC verification experience with fabric/interconnect/NoC, strong SystemVerilog and UVM skills, knowledge of interconnect protocols (AMBA AXI, CHI), scripting (Python, Perl, TCL), and degree in computer/electrical engineering or equivalent experience.
SystemVerilog, UVM, AMBA AXI, CHI, Python, Perl, TCL, Palladium, Veloce, SVA
Job PostingView all
5d
Save
Mark Applied
Hide
SoC Interconnect and Fabric RTL Designer
San Jose, California, United States
HybridFull Time
TylSemi
TylSemi: Building chiplet-native infrastructure for high-performance AI systems.
8+ YOEBS/MS in EE/Computer Engineering, 8+ years digital IC design with 4+ years owning on-chip interconnect/NoC or fabric architecture; strong SystemVerilog, AXI/CHI/NoC, CDC, integration, and register-map experience.
AXI4, AXI4-Lite, AXI-Stream, CHI, AMBA CHI, ACE, NoC, SystemVerilog, SystemRDL, IP-XACT
Job PostingView all
3mo
Save
Mark Applied
Hide
Technical Lead, Design Verification
Santa Clara, California, United States
$159k-$238k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
Lead verification for SoCs, develop UVM environments, mentor engineers, strong SystemVerilog, Python, ARM/NoC expertise.
SystemVerilog, UVM, Python, Xcelium, Questa, VCS
Job PostingView all
2w
Save
Mark Applied
Hide
Manager of Field Applications Engineering, USA
Santa Clara or Austin
OnsiteFull Time
Baya Systems
Baya Systems: Designs semiconductor fabric IP and chiplet design software.
10+ YOE5+ MgmtBachelor's in EE/CE/STEM required; 10+ years in semiconductor/silicon IP/networking and 5+ years managing customer-facing engineering teams; deep NoC/AMBA/PCIe/CXL knowledge and EDA tool familiarity.
Synopsys, Cadence, Siemens
Job PostingView all
2mo
Save
Mark Applied
Hide
AI/ML ASIC Architect
Milpitas, California, United States
$137k-$226k/yr HybridFull Time
Sandisk
SandiskNasdaq: SNDK: Designs and manufactures flash memory and data storage products.
7+ YOE7+ yrs experience in Computer/Electrical Engineering; 5+ yrs for Masters; 3+ yrs for PhD; architecture authoring experience; PCIe/UCIe/CXL, DMA subsystems know-how.
PCIe, UCIe, CXL, NoC, DMA, HBM, NVLink, CUDA
Job PostingView all
2mo
Save
Mark Applied
Hide
Senior Performance Modeling Architect, CPU Fabric and LLC
Santa Clara, California, United States
$152k-$288k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
5+ YOEMaster's or PhD in CE/EE/CS (or equivalent) with 5+ years experience; deep knowledge of CPU microarchitecture, cache coherency, NoC topologies; experience with C++/SystemC and Python; benchmarking and performance analysis experience.
C++, SystemC, Python, SPEC, MLPerf
Job PostingView all
1mo
Save
Mark Applied
Hide
Lead SoC Architect - India
Sunnyvale or India
OnsiteFull Time
Bolt Graphics
Bolt Graphics: Designing high-efficiency graphics processors for professional rendering and simulation.
10+ YOERequires Bachelor's or Master's in EE/CE/CS, 10+ years SoC/ASIC experience, expertise in SoC subsystems (CPU/GPU/NPU, NoC, memory, PCIe), C/C++/SystemC modeling, RTL knowledge, and on-site presence in Sunnyvale.
C, C++, SystemC, Linux
Job PostingView all

Explore Jobs

Expand Your Job Search