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685 package jobs at 242 companies in San Francisco, CA

1mo
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Package Screener
Fremont, California, United States
$25/hr OnsitePart Time
Andy Frain Services
Andy Frain Services: Provides professional security and event crowd management services.
Valid CA Guard Card and reliable transportation required; perform package screening using X-ray and trace detection, maintain logs and equipment; late afternoon/evening availability.
X-ray, explosive trace detection
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2w
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PACKAGE HANDLER
Hayward, California, United States
$18/hr OnsitePart Time
GLS US
GLS USLondon Stock Exchange: IDS: Provider of regional parcel and freight delivery services.
Must be at least 18, able to lift up to 75 lbs, stand for prolonged periods, work in varying weather, follow instructions, and perform package sorting and loading tasks safely.
forklift, pallet jack
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1mo
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Package Handler
Fremont, California, United States
$20/hr OnsiteFull Time
OnTrac
OnTrac: Provides last-mile delivery services for e-commerce retailers.
Must be able to stand for long periods, lift/move packages averaging 50 lbs (up to 75 lbs occasionally), work in varied warehouse temperatures, be at least 18 years old, and have basic English for safety and instructions.
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1w
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Package Layout Engineer
Mountain View, California, United States
$200k-$275k/yr OnsiteFull Time
DensityAI
DensityAI: Designing custom AI hardware accelerators for large language models.
8+ YOERequires 8+ years of advanced package layout experience, including multi-die 2.5D/3D packages, substrate and interposer routing, package DRC/LVS, and collaboration with physical design, SI/PI, thermo-mechanical, and OSAT teams.
Cadence Allegro Package Designer, SiP Layout, Siemens Xpedition Package Designer, DRC, LVS, AI
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4w
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Package Concierge - Chorus
San Francisco, California, United States
$25-$30/hr OnsiteFull Time
Align Real Estate Management
Align Real Estate Management: Manages and develops high-end luxury residential communities
Organized, customer-focused individual with strong communication and interpersonal skills; ability to handle packages, work independently or on a team, and use basic technology.
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2w
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Package Design Engineer
San Jose or Austin or Fort Collins
$122k-$195k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
6+ YOEBSEE with 8+ years or MSEE with 6+ years in flip-chip BGA package design; knowledge of package signal and power integrity; Cadence APD and Cadence SKILL experience preferred; project management and collaboration skills.
Cadence APD, Cadence SKILL
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2mo
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Sr. Package Designer
San Francisco, California, United States
$90k-$138k/yr HybridFull Time
Benefit Cosmetics
Benefit Cosmetics: Sells high-end makeup products and provides professional eyebrow styling.
6+ YOE6+ years design experience (packaging a plus), strong concepting and print production knowledge, advanced industry-standard software skills, project management proficiency, sustainability experience, and ability to collaborate cross-functionally.
Accolade, Proof HQ
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1mo
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Associate Package Development Engineer
San Francisco, California, United States
$35-$43/hr HybridFull Time
LVMH
LVMHEuronext Paris: MC: A diversified luxury conglomerate managing fashion, spirits, and beauty brands.
1+ YOEB.S. in Packaging Engineering or related, 1+ year packaging/manufacturing experience, knowledge of secondary components, printing/color matching, package testing, technical drawings and project timeline management.
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3w
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Principal Package Design Engineer
San Jose, California, United States
$195k-$240k/yr HybridFull Time
Renesas Electronics
Renesas ElectronicsTokyo Stock Exchange: 6723: Designs and manufactures semiconductors for automotive and industrial systems.
5+ YOEMSc/PhD in engineering, 5+ years semiconductor packaging experience, expertise in advanced packaging architectures, reliability testing, thermal/mechanical/electrical analysis, OSAT collaboration, and project leadership.
Cadence Allegro Package Designer, Solid works, ANSYS, COMSOL, JMP, Minitab
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1w
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Lead Package Assembly Integrator
Mountain View, California, United States
$218k-$317k/yr HybridFull Time
Lightmatter
Lightmatter: Develops photonic processors and interconnects for AI data centers
MS or PhD in mechanical engineering, materials science, or related engineering; experience developing wafer-scale packaging assembly processes, 2D/3D packaging, test vehicles, fiber attachment, and thermal, mechanical, and reliability solutions.
3D, RDL
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Package Design Engineer - Staff
Santa Clara or San Diego
$154k-$253k/yr OnsiteFull Time
Qualcomm
QualcommNASDAQ: QCOM: Designs and manufactures semiconductors and wireless telecommunications products.
5+ YOEExperience in IC package/SIP physical design, Cadence APD/Allegro proficiency, familiarity with SI/PI tools (HFSS, PowerSI, Q3D), package verification and CAD tool development; master\u0002s preferred with 5+ years.
Cadence APD, Cadence Allegro, PCB Editor, Advanced Package Designer, APD/SiP, XtractIM, PowerSI, HFSS, Q3D, Calibre
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1w
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Package Design & Layout Engineer
Palo Alto, California, United States
OnsiteFull Time
Cspeed IO
Cspeed IO: A stealth startup developing next-generation optical semiconductor solutions for AI infrastructure.
6+ YOE6+ years IC package physical design experience, BS/MS in electrical engineering, expertise in package layout tools, multi-die packaging, substrate stack-ups, DFM/DF A closure, and English fluency.
Cadence Allegro Package Designer, APD+, Siemens Xpedition Package Designer, Synopsys IC Package, SKILL, Python, Cadence Sigrity, PowerSI, Ansys, Virtuoso, KLayout, AutoCAD, Cadence Integrity 3D-IC
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Package Design Engineer
Sunnyvale, California, United States
$163k-$237k/yr OnsiteFull Time
Google
GoogleNASDAQ: GOOGL: Provides online search, advertising, cloud computing, and consumer electronics.
8+ YOEBachelor's in engineering or equivalent, 8 years experience in chip package substrate design using Cadence APD or Mentor Expedition, EM/DFM/taping experience, design automation and scripting, B.S./M.S./PhD preferred.
Cadence APD, Mentor Expedition, CAD
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2w
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Package Design Methodology Engineer
Santa Clara or Austin or California
$136k-$265k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
5+ YOEBS or equivalent and 5+ years developing package design flows; strong Python/C++ skills; experience applying AI/ML and LLMs in engineering workflows; solid VLSI package design fundamentals.
Python, C++, LLMs, EDA, AI/ML
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2mo
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Package Development/NPI Engineer
San Jose or Chandler
$180k-$301k/yr OnsiteFull Time
MediaTek
MediaTekTaiwan Stock Exchange: 2454: Designs and develops system-on-chip solutions for electronic devices.
8+ YOE8+ years in package development and NPI for semiconductors; expertise in advanced packaging (EMIB, 2.5D/3D/3.5D, FCBGA, HBM); qualification, reliability, failure analysis, yield improvement, and cross-functional project management.
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2w
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Package Design Methodology Engineer
Santa Clara or Austin or United States
$136k-$265k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
5+ YOEBS in CS/EE or equivalent,5+ years developing package design flows/methodologies,proficiency in Python and/or C++,knowledge of VLSI package electrical fundamentals,experience applying AI/ML or LLMs in engineering workflows.
Python, C++, LLMs, EDA
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3mo
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IC Package Design Engineer
Los Angeles or San Francisco or Austin
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
Bachelor's degree; IC package physical design experience; Cadence Allegro/Mentor Xpedition; high-speed interfaces; SI/PI; DFM; scripting in Python/Perl/TCL.
Cadence Allegro, Mentor Xpedition, Calibre, CAM350, HFSS, PowerSI, RLGC, S-parameters, Python, Perl, TCL
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1mo
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Senior Package Reliability Engineer
San Jose, California, United States
$167k-$240k/yr OnsiteFull Time
Altera
Altera: Manufacturer of field-programmable gate arrays and programmable logic devices.
8+ YOEMaster's in engineering or related plus 8+ years in semiconductor package thermal/thermomechanical analysis; experience with Ansys/Abaqus/COMSOL and Python; reliability statistics and failure analysis skills.
Ansys, Abaqus, COMSOL, Python
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3w
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IC Package Design Engineer
San Jose, California, United States
$153k-$219k/yr HybridFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
3+ YOEBachelor's (5+ years) or Master’s (3+ years) in Electrical Engineering or related field; experience in package/PCB/high-speed design, power delivery, and EDA tools; scripting (Python, Perl, TCL, shell) and strong collaboration skills.
EDA, Python, Perl, TCL, Shell
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Sr. Package Layout Engineer, Annapurna Labs - AI Silicon Packaging
Tempe or Austin or Cupertino
$159k-$248k/yr OnsiteFull Time
Amazon
AmazonNASDAQ: AMZN: Global online retail and cloud computing technology provider.
10+ YOEBachelor's in EE or related, 10+ years IC package layout and physical design experience, expertise with advanced packaging (2.5D/3D, WLP, RDL, TSV), package DRC/DFM, and collaboration with SI/PI and manufacturing teams.
Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, Python, TCL, Skill, Ravel
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