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99 packaging design engineer jobs at 49 companies in Tracy, CA

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Packaging Design Engineer
San Jose or San Diego
HybridFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
Experienced package engineer with CAD/simulation tool proficiency, package/PCB layout and power integrity expertise, scripting ability, and engineering degree.
Cadence, SKILL, Ansys, AutoCAD
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3mo
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Packaging Design Engineer I
San Jose or Hayward or Texas
OnsiteFull Time
TransPak: Packaging solutions provider
2+ YOEBachelor’s in mechanical/manufacturing/industrial/packaging engineering; 2-3 years mechanical/structural design experience; CAD (SolidWorks/AutoCAD); GD&T knowledge; packaging design and testing experience; strong communication.
SolidWorks, AutoCAD, NX, BOM, 3D modeling, 2D drawings, GD&T
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3mo
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Senior, Packaging Design Engineer
Sunnyvale, California, United States
$163k-$199k/yr OnsiteFull Time
Intuitive
IntuitiveNASDAQ: ISRG: Robotic-assisted systems for minimally invasive surgery.
8+ YOE8+ years in medical device packaging design; BS in Packaging/Mechanical/Industrial Engineering; experience with thermoforming, pouch sealing, ISO11607, CFR 820; CAD (SolidWorks); travel; strong communication.
SolidWorks, FEA, Packaging testing tools, MS Office
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1mo
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Advanced Packaging Design Engineer
Santa Clara or Chandler
$192k-$287k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
5+ YOEBS/MS/PhD in engineering,5-10 years advanced packaging design experience, expertise with Cadence APD, high-speed interfaces, substrate and assembly processes, and cross-functional collaboration.
Cadence APD, AutoCAD
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1w
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Packaging Design Engineer, Platforms Infrastructure Engineering
Sunnyvale, California, United States
$159k-$230k/yr OnsiteFull Time
Google
GoogleNASDAQ: GOOGL: Provides online search, advertising, cloud computing, and consumer electronics.
5+ YOEBachelor's degree or equivalent practical experience, 5+ years in hardware or consumer-goods packaging design, ISTA and ASTM D4169 experience, and CAD proficiency. CPP, master's degree, and 8 years' experience preferred.
ISTA, ASTM D4169, computer-aided design (CAD), Creo, NX, SolidWorks, TOPS, CAPE, FEA
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2w
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Senior Packaging Engineer
Palo Alto, California, United States
$211k-$224k/yr OnsiteFull Time
Wing
WingNASDAQ: GOOGL: Autonomous drone delivery service for small packages and logistics
5+ YOERequires 5+ years in packaging, mechanical design, or industrial design; advanced packaging and structural mechanics knowledge; CAD and palletization software expertise; testing, documentation, collaboration, and travel ability.
ArtiosCAD, Esko, SolidWorks, CATIA, CAPE, TOPS, CAD
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2mo
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Sr Packaging Engineer
Santa Clara, California, United States
$134k-$184k/yr OnsiteFull Time
Applied Materials
Applied MaterialsNASDAQ: AMAT: Manufacturers of equipment for semiconductor and display production.
Experience in packaging engineering including supplier management, test plan development and lab testing, Design for Transportability (DFT), packaging standards, continuous improvement, and ability to lead projects.
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Sr Packaging Engineer
Santa Clara, California, United States
$134k-$184k/yr OnsiteFull Time
Applied Materials
Applied MaterialsNASDAQ: AMAT: Produces equipment and services for chip and display manufacturing.
Packaging engineering experience with supplier management, test plan development, Design For Transportability (DFT), standards development, continuous improvement, and ability to train others; travel ~10%.
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2mo
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Manufacturing Design Engineer (MDE) - Packaging
Cupertino, California, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
Managing R&D, selection, and implementation of manufacturing processes for consumer packaging parts and assemblies; strong product and process engineering skills.
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1w
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Packaging Tech Lead Design Engineer
San Jose, California, United States
$185k-$240k/yr OnsiteFull Time
Astera Labs
Astera LabsNASDAQ: ALAB: Designs connectivity solutions for cloud and AI infrastructure.
5+ YOEBachelor's degree in electrical or computer engineering and 5+ years of digital design experience, including a full chip from specification to tapeout. Requires Verilog/SystemVerilog, RTL, synthesis, timing closure, CDC, lint, and low-power expertise.
Verilog, SystemVerilog, RTL, CDC, DFT, BIST, PCIe, CXL, Ethernet, NVLink, UALink, UCIe, COSMOS, SoC
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Advanced Packaging Engineer
Mountain View, California, United States
$200k-$350k/yr OnsiteFull Time
DensityAI
DensityAI: Designing custom AI hardware accelerators for large language models.
10+ YOE10+ years in advanced multi-die packaging (SiP, CoWoS, EMIB, interposers); expertise in design layout, SI/PI, thermo-mechanical tradeoffs; hands-on with packaging flows for 2.5D/3D; ability to collaborate with architects; DFT/RTL/PD optional.
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Principal Packaging Engineer
Palo Alto or United States or Canada
$180k-$240k/yr HybridFull Time
Delos Data
Delos Data: Building specialized interconnects and infrastructure optimized for AI inference.
B.S./M.S. in EE or related, expertise in multi-die package design and UCIe, substrate and SI/PI knowledge, experience with TSMC/OSAT and managing subcontractors; HFSS/Sigrity familiarity a plus.
HFSS, Sigrity, UCIe
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1mo
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Principal Packaging Engineer, Optical Interfaces
Santa Clara, California, United States
$145k-$255k/yr OnsiteFull Time
nEye Systems
nEye Systems: Develops MEMS-based silicon photonics optical circuit switches for data centers.
10+ YOE10+ years packaging design experience for optical/photonic components, experience with PIC edge coupling, reliability engineering, CAD and FEA usage, and working with contract manufacturers.
CAD, FEA
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Staff Semi Packaging Engineer
San Jose, California, United States
$130k-$188k/yr OnsiteFull Time
Analog Devices
Analog DevicesNASDAQ: ADI: Designs and manufactures semiconductors for signal processing and power management.
3+ YOEMaster's in a relevant engineering field + ≥3 years industrial IC/package experience; expertise in analog IC package/module design, reliability and BOM selection, CAD modeling, and process development (FMEA, SPC, DOE); OSAT collaboration experience.
CAD
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2w
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Package Layout Design Engineer , Annapurna Labs - AI Silicon Packaging
Tempe or Austin or Cupertino
$136k-$213k/yr OnsiteFull Time
Amazon
AmazonNASDAQ: AMZN: Global online retail and cloud computing technology provider.
5+ YOEBachelor's degree in electrical engineering or related field and 5+ years of IC package layout and physical design experience. Requires package layout tools, advanced packaging, DFM, and physical verification expertise.
Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, Python, Perl, ARM, TCL, Skill, Ravel, DRC
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2mo
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Sr Principal Laser Packaging Engineer
Fremont, California, United States
$200k-$280k/yr OnsiteFull Time
Koch Inc.
Koch Inc.: Operates global manufacturing, refining, and industrial technology businesses.
10+ YOEPhD in a related field, 10+ years R&D experience in optoelectronic package design transferred to manufacturing, submicron optical alignment, FEA/thermal design, GR-468 qualification, NPI, and strong supplier/customer communication.
Finite Element Analysis (FEA), CFD
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Package Design Methodology Engineer
Santa Clara or Austin or California
$136k-$265k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
5+ YOEBS or equivalent and 5+ years developing package design flows; strong Python/C++ skills; experience applying AI/ML and LLMs in engineering workflows; solid VLSI package design fundamentals.
Python, C++, LLMs, EDA, AI/ML
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4w
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Package Design Engineer
San Jose or Austin or Fort Collins
$122k-$195k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
6+ YOEBSEE with 8+ years or MSEE with 6+ years in flip-chip BGA package design; knowledge of package signal and power integrity; Cadence APD and Cadence SKILL experience preferred; project management and collaboration skills.
Cadence APD, Cadence SKILL
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Package Design & Layout Engineer
Palo Alto, California, United States
OnsiteFull Time
Cspeed IO
Cspeed IO: A stealth startup developing next-generation optical semiconductor solutions for AI infrastructure.
6+ YOE6+ years IC package physical design experience, BS/MS in electrical engineering, expertise in package layout tools, multi-die packaging, substrate stack-ups, DFM/DF A closure, and English fluency.
Cadence Allegro Package Designer, APD+, Siemens Xpedition Package Designer, Synopsys IC Package, SKILL, Python, Cadence Sigrity, PowerSI, Ansys, Virtuoso, KLayout, AutoCAD, Cadence Integrity 3D-IC
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1mo
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Package Design Methodology Engineer
Santa Clara or Austin or United States
$136k-$265k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
5+ YOEBS in CS/EE or equivalent,5+ years developing package design flows/methodologies,proficiency in Python and/or C++,knowledge of VLSI package electrical fundamentals,experience applying AI/ML or LLMs in engineering workflows.
Python, C++, LLMs, EDA
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