88 packaging designer jobs at 48 companies in Capitola, CA
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Senior Packaging Engineer
Palo Alto, California, United States
$211k-$224k/yrOnsiteFull Time
WingNASDAQ: GOOGL: Autonomous drone delivery service for small packages and logistics
5+ YOERequires 5+ years in packaging, mechanical design, or industrial design; advanced packaging and structural mechanics knowledge; CAD and palletization software expertise; testing, documentation, collaboration, and travel ability.
DensityAI: Designing custom AI hardware accelerators for large language models.
10+ YOE10+ years in advanced multi-die packaging (SiP, CoWoS, EMIB, interposers); expertise in design layout, SI/PI, thermo-mechanical tradeoffs; hands-on with packaging flows for 2.5D/3D; ability to collaborate with architects; DFT/RTL/PD optional.
Applied MaterialsNASDAQ: AMAT: Produces equipment and services for chip and display manufacturing.
Packaging engineering experience with supplier management, test plan development, Design For Transportability (DFT), standards development, continuous improvement, and ability to train others; travel ~10%.
Delos Data: Building specialized interconnects and infrastructure optimized for AI inference.
B.S./M.S. in EE or related, expertise in multi-die package design and UCIe, substrate and SI/PI knowledge, experience with TSMC/OSAT and managing subcontractors; HFSS/Sigrity familiarity a plus.
IntuitiveNASDAQ: ISRG: Robotic-assisted systems for minimally invasive surgery.
8+ YOE8+ years in medical device packaging design; BS in Packaging/Mechanical/Industrial Engineering; experience with thermoforming, pouch sealing, ISO11607, CFR 820; CAD (SolidWorks); travel; strong communication.
SolidWorks, FEA, Packaging testing tools, MS Office
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
Experienced package engineer with CAD/simulation tool proficiency, package/PCB layout and power integrity expertise, scripting ability, and engineering degree.
nEye Systems: Develops MEMS-based silicon photonics optical circuit switches for data centers.
10+ YOE10+ years packaging design experience for optical/photonic components, experience with PIC edge coupling, reliability engineering, CAD and FEA usage, and working with contract manufacturers.
Analog DevicesNASDAQ: ADI: Designs and manufactures semiconductors for signal processing and power management.
3+ YOEMaster's in a relevant engineering field + ≥3 years industrial IC/package experience; expertise in analog IC package/module design, reliability and BOM selection, CAD modeling, and process development (FMEA, SPC, DOE); OSAT collaboration experience.
Gilead SciencesNASDAQ: GILD: Develops and sells medicines for life-threatening infectious diseases.
10+ YOEBachelor's degree in packaging or engineering plus 10 years of relevant industry experience and cGMP experience. Requires packaging engineering leadership, combination products, design controls, risk management, and regulatory knowledge.
ISO 11607, ISO 14971, FDA, EU MDR, 21 CFR, ASTM, ISTA, Workday
Astera LabsNASDAQ: ALAB: Designs connectivity solutions for cloud and AI infrastructure.
10+ YOEPh.D. or M.S. in EE, Physics, Materials Science, Mechanical Engineering, or related field; 10+ years in photonic packaging or related areas; strong expertise in high-speed packaging, thermal management, and optomechanical design.
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
5+ YOEBS/MS/PhD in engineering,5-10 years advanced packaging design experience, expertise with Cadence APD, high-speed interfaces, substrate and assembly processes, and cross-functional collaboration.
Koch Inc.: Operates global manufacturing, refining, and industrial technology businesses.
10+ YOEPhD in a related field, 10+ years R&D experience in optoelectronic package design transferred to manufacturing, submicron optical alignment, FEA/thermal design, GR-468 qualification, NPI, and strong supplier/customer communication.
5+ YOEBachelor's degree or equivalent practical experience, 5+ years in hardware or consumer-goods packaging design, ISTA and ASTM D4169 experience, and CAD proficiency. CPP, master's degree, and 8 years' experience preferred.
AmazonNASDAQ: AMZN: Global online retail and cloud computing technology provider.
9+ YOE9+ years design or packaging program experience; end-to-end packaging development, BOM and POD labeling knowledge; strong cross-functional program management and travel availability.
Bill of Material (BOM), Print On Demand (POD), scrum
CoherentNYSE: COHR: Manufactures lasers, engineered materials, and optical networking components.
2+ YOEBS/MS in telecom/optomechanical engineering, physics or related; minimum 2 years' related experience; SolidWorks and MS Office proficiency; experience with telecom fibers, materials selection, packaging design, testing, and manufacturing transfer.
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
Design and execute structural packaging for Apple products while protecting products during shipping and advancing sustainability goals; collaborate across design, marketing, environmental, and operations teams.
NetflixNASDAQ: NFLX: Provider of global streaming entertainment and video content.
10+ YOE10+ years software development experience (5+ years on inventory management); expertise in yield optimization, dynamic pricing, auction mechanics, rate card and packaging systems; API and data model design; technical leadership and strong communication.
ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)
San Jose or Research Triangle Park or Acton or Dallas or Tempe or Cary or Carlsbad or Colorado Springs
$184k-$264k/yrRemoteFull Time
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
3+ YOEBachelor's/MS/PhD in Electrical Engineering with 3+ to 8+ years SI/PI experience; expertise in high-speed design, SI/PI simulation, layout review, SPICE; mentoring and leadership experience.
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
8+ YOEBS/MS/PhD in EE or equivalent, 8+ years in signal integrity/high-speed interconnects, SerDes/channel design, electromagnetics, simulation-to-measurement correlation using VNA/TDR/scope, and experience with industry SI tools.