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343 physical design engineer jobs at 123 companies in San Jose, CA

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Physical Design Engineer
Sunnyvale, California, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
Experienced engineer to perform PHY physical design, collaborate with architecture/CAD/timing/logic teams, and deliver high-quality PHY implementations.
CAD
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1w
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Physical Design Engineer
San Jose, California, United States
$119k-$169k/yr OnsiteFull Time
Altera
Altera: Manufacturer of field-programmable gate arrays and programmable logic devices.
3+ YOEBachelor's degree in a technical discipline and 3+ years of semiconductor physical design experience, including RTL-to-GDSII implementation, physical design flows, timing analysis, and verification/signoff.
RTL, GDSII, Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Formal Equivalence Checking (LEC), Power Integrity, IR Drop, Electromigration (EM), Electrical Rule Checking (ERC), Design Rule Checking (DRC), Layout Versus Schematic (LVS), Design-for-Test (DFT), Tcl, Python, Perl, Shell, UPF, CPF, Synopsys, Cadence, Siemens EDA
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2mo
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Physical Design Engineer
Mountain View, California, United States
$230k-$400k/yr OnsiteFull Time
DensityAI
DensityAI: Designing custom AI hardware accelerators for large language models.
8+ YOE8+ years in physical design for high-performance chips at advanced nodes, expert across full physical design flow, hands-on with industry PD and signoff tools, and ability to collaborate with architects, RTL designers, EDA vendors, and foundries.
Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, Tempus
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1mo
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Physical Design Engineer
San Jose, California, United States
$150k-$250k/yr OnsiteFull Time
Fortell
Fortell: AI-powered hearing aids providing enhanced speech clarity.
7+ YOE7+ years physical design experience (synthesis, PnR, STA, timing convergence, physical verification); Bachelor's in EE/CE/CS or equivalent experience; proficiency with Innovus, Tempus, Quantus, TCL; experience with EM/IR, PDN, LEC and sub-7nm/SoC design.
Innovus, Tempus, Quantus, TCL, Cadence, Synopsys
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3mo
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Physical Design Engineer
Austin or Fort Collins or Santa Clara
$100k-$500k/yr HybridFull Time
Tenstorrent
Tenstorrent: Designs and manufactures AI processors and RISC-V CPU solutions.
BS/MS/PhD in EE/ECE/CE/CS with experience in synthesis, PnR, timing closure; proficient with FusionCompiler, PrimeTime, RedHawk; scripting Tcl, Perl, Python; knowledge of low-power design; drive physical design from architecture to signoff.
FusionCompiler, PrimeTime, RedHawk, Tcl, Perl, Python
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2mo
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Physical Design Engineer
Sunnyvale, California, United States
$230k-$280k/yr OnsiteFull Time
Cerebras Systems
Cerebras SystemsNasdaq: CBRS: Manufactures specialized computer chips designed for AI.
10+ YOE10+ years physical design experience; expertise in full-chip physical verification, DRC/LVS resolution with ICV or Calibre, IR/EM analysis, 3D/2.5D packaging and die stacking; scripting with Tcl and Python; familiarity with Synopsys tools.
Synopsys, ICV, Calibre, Tcl, Python
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Principal Physical Design Engineer
San Jose, California, United States
$185k-$230k/yr OnsiteFull Time
Astera Labs
Astera LabsNASDAQ: ALAB: Designs connectivity solutions for cloud and AI infrastructure.
8+ YOEBachelor's degree in engineering, 8+ years of physical design experience with advanced-node tapeouts, expertise in synthesis, place-and-route, CTS, timing closure, low-power design, and Tcl/Python automation.
Synopsys Fusion Compiler, ICC2, Cadence Innovus, PrimeTime, Tcl, Python, UPF, CPF, LVS, DRC, ERC, STA, RTL, DFT, GDS, PCIe, UALink, UCIe
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Senior Physical Design Engineer
Hillsboro or Redmond or Mountain View or Raleigh or Austin
$120k-$235k/yr HybridFull Time
Microsoft
MicrosoftNASDAQ: MSFT: Develops software, services, devices, and cloud computing solutions.
1+ YOERequires a relevant engineering or computer science degree and 1–5+ years of technical engineering experience; preferred experience includes semiconductor physical design, tape-outs, low-power methods, and signoff workflows.
synthesis, place-and-route, clock construction, CTS, RTL, DFT, RTL to GDS, EMIR, formal equivalence, low-power verification
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Senior Physical Design Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
E-Space
E-Space: Builds sustainable LEO satellite networks for global IoT connectivity
8+ YOESenior Physical Design Engineer with 8+ years in ASIC/SoC physical design; Cadence Innovus expertise; floorplanning, CTS, routing; timing closure; scripting (Python/Tcl).
Cadence Innovus, Synopsys ICC2, Mentor Calibre, Tcl, Python, Verilog, SystemVerilog, UVM, VHDL
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Senior Physical Design Engineer
Santa Clara, California, United States
$82k-$193k/yr OnsiteFull Time
Capgemini
CapgeminiEuronext Paris: CAP: Provides global IT consulting and digital transformation services.
10+ YOERequires 10+ years in physical design, advanced digital or mixed-signal IC implementation, physical verification, timing analysis, tape-out, and EDA tools including Virtuoso, Calibre, or RedHawk.
Virtuoso, Calibre, RedHawk, EDA, SDF
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Principal Physical Design Engineer
San Jose or Irvine
$150k-$250k/yr OnsiteFull Time
Celero Communications
Celero Communications: Developing high-performance coherent DSP technology for AI connectivity.
5+ YOE5+ years of ASIC physical design experience, advanced-node tapeout expertise, EDA tool proficiency, and expertise in synthesis, power analysis, EM/IR cleanup, timing closure, and physical verification.
System-on-Chips (SoCs), RTL, GDSII, Static Timing Analysis (STA), Design Rule Checking (DRC), Layout Versus Schematic (LVS), Tcl, Python, Perl, Cadence Innovus, Cadence Tempus, Cadence Voltus, Cadence Pegasus, Calibre
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2mo
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Principal Physical Design Engineer
Sunnyvale, California, United States
$174k-$353k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides global edge-to-cloud technology solutions and IT infrastructure services.
7+ YOEBS/MS in EE/CompEng, 7+ years ASIC physical design experience, strong expertise with Cadence Innovus and Synopsys Fusion Compiler, scripting in Tcl/Python/Linux shell, and physical signoff knowledge.
Cadence Innovus, Synopsys Fusion Compiler, Tcl, Python, Make, Linux shell, PrimeTime, StarRC, Voltus, RedHawk, Calibre, Git, Perforce
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2mo
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Principal Physical Design Engineer
Sunnyvale, California, United States
$174k-$353k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Providing global edge-to-cloud infrastructure and IT solutions for businesses.
7+ YOEBS/MS in EE/CE or related, 7+ years ASIC physical design/methodology experience, expertise with Cadence Innovus and/or Synopsys Fusion Compiler, strong scripting (Tcl, Python, Linux shell), and physical signoff knowledge.
Cadence Innovus, Synopsys Fusion Compiler, Tcl, Python, Make, Linux shell, PrimeTime, StarRC, Voltus, RedHawk, Calibre, Git, Perforce
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3mo
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Physical Design Engineer II (Silicon Engineering)
Bastrop or Irvine or Sunnyvale
$155k-$185k/yr OnsiteFull Time
SpaceX
SpaceX: Designs and launches advanced rockets and satellite internet constellations.
3+ YOEBachelors in engineering; 3+ years RTL-to-GDSII physical design or flow development.
EDA tools, RTL-to-GDSII, Scripting (Python, TCL, Bash)
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1w
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CPU Physical Design Engineer
Austin or Mountain View
$138k-$197k/yr OnsiteFull Time
Google
GoogleNASDAQ: GOOGL: Provides online search, advertising, cloud computing, and consumer electronics.
4+ YOEBachelor's degree or equivalent practical experience, 4 years of digital physical design implementation, and experience with synthesis, place and route, timing closure, and signoff tools.
Tcl, Python, Static Timing Analysis (STA), Place and Route (PnR), EMIR
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Physical Design Engineer
Austin or Fort Collins or Santa Clara
$100k-$500k/yr HybridFull Time
Tenstorrent
Tenstorrent: A technology developing high-performance AI computing platforms, CPUs, and semiconductor solutions.
BS/MS/PhD in EE/ECE/CE/CS; proven synthesis, PnR, timing closure, and tapeout experience; Innovus, PrimeTime, RedHawk, Tcl, Perl, and Python expertise; advanced-node and low-power design knowledge.
Innovus, PrimeTime, RedHawk, Tcl, Perl, Python
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1mo
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Sr. Physical Design Engineer
San Jose, California, United States
OnsiteFull Time
Lumilens
Lumilens: Designs photonic interconnects for AI supercomputing infrastructure.
8+ YOE8+ years physical design experience for advanced TSMC nodes (5nm/3nm), Bachelor’s degree in EE or related, strong floorplanning/placement/CTS/routing/signoff skills, and scripting in Tcl/Python/Perl.
Synopsys ICC2, RedHawk SC, Cadence Innovus, Voltus, Simens Calibre, Tcl, Python, Perl
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Physical Design Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
12+ YOEBachelor's degree in Electrical Engineering or Computer Science with 12+ years' related experience, or master's with 10+ years. Requires IC, package, and PCB layout tools plus TCL and Python scripting.
TCL, Python
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2mo
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Principal Physical Design Engineer
Sunnyvale, California, United States
$174k-$353k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides edge-to-cloud IT infrastructure and platform services.
7+ YOEBS/MS in EE/CE or related, 7+ years in ASIC physical design flows, expertise with Cadence Innovus or Synopsys Fusion Compiler, scripting in Tcl/Python/Linux shell, experience with timing, power, signoff, and flow automation.
Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, StarRC, Voltus, RedHawk, Calibre, Tcl, Python, Linux shell, Git, Perforce, Make
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3mo
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Senior Physical Design Engineer
Santa Clara, California, United States
$136k-$265k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
2+ YOEBS or MS in Electrical or Computer Engineering; 5+ years (BS) or 2+ years (MS) in physical design; proficiency with Synopsys or Cadence P&R tools; ability to develop methodologies; DFT knowledge a plus.
Synopsys, Cadence, Place and Route Tools
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