3mo
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Physical Design Engineer
Cupertino or United States
OnsiteFull Time
Bachelor's degree in Electrical Engineering with strong physical design experience.
4d
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Physical Design Engineer
Colorado Springs, Colorado, United States
$129k-$207k/yr OnsiteFull Time
12+ YOEBachelor's in Electrical/Electronics Engineering, 12+ years' RTL-to-tapeout physical design experience, TCL/PERL scripting, EDA tool proficiency, B2B communication and timing closure expertise.
TCL, PERL, EDA Tools
2mo
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Physical Design Engineer
Mountain View, California, United States
$230k-$400k/yr OnsiteFull Time
8+ YOE8+ years in physical design for high-performance chips at advanced nodes, expert across full physical design flow, hands-on with industry PD and signoff tools, and ability to collaborate with architects, RTL designers, EDA vendors, and foundries.
Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, Tempus
1mo
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Physical Design Engineer
Austin or New York City or New York or Washington or Illinois or United States or Canada
$137k-$201k/yr OnsiteFull Time
7+ YOEDegree in Electrical/Computer Engineering plus multi-year ASIC/physical design experience; experience with RTL-to-GDSII flow, STA, floorplanning, timing closure, and EDA tools (Innovus, PrimeTime, Tempus, Calibre, Redhawk/Voltus).
Innovus, Tempus, PrimeTime, Tweaker, Redhawk, Voltus, Calibre, Pegasus, Python
2w
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Physical Design Engineer
San Jose, California, United States
$150k-$250k/yr OnsiteFull Time
7+ YOE7+ years physical design experience (synthesis, PnR, STA, timing convergence, physical verification); Bachelor's in EE/CE/CS or equivalent experience; proficiency with Innovus, Tempus, Quantus, TCL; experience with EM/IR, PDN, LEC and sub-7nm/SoC design.
Innovus, Tempus, Quantus, TCL, Cadence, Synopsys
1mo
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Physical Design Engineer
Sunnyvale, California, United States
$230k-$280k/yr OnsiteFull Time
10+ YOE10+ years physical design experience; expertise in full-chip physical verification, DRC/LVS resolution with ICV or Calibre, IR/EM analysis, 3D/2.5D packaging and die stacking; scripting with Tcl and Python; familiarity with Synopsys tools.
Synopsys, ICV, Calibre, Tcl, Python
2mo
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Physical Design Engineer
Austin or Fort Collins or Santa Clara
$100k-$500k/yr HybridFull Time
BS/MS/PhD in EE/ECE/CE/CS with experience in synthesis, PnR, timing closure; proficient with FusionCompiler, PrimeTime, RedHawk; scripting Tcl, Perl, Python; knowledge of low-power design; drive physical design from architecture to signoff.
FusionCompiler, PrimeTime, RedHawk, Tcl, Perl, Python
2w
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Physical Design Engineer
Beaver Brook or Phoenix
$122k-$200k/yr OnsiteFull Time
2+ YOEExperience implementing physical design flows for custom IP/SoC, proficiency with EDA tools, RTL/GDS knowledge, scripting (TCL), and 2+ years of relevant experience with a relevant degree.
industry-standard EDA tools, TCL, RTL, GDS
1mo
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Physical Design Engineer
Westford, Massachusetts, United States
$116k-$219k/yr OnsiteFull Time
3+ YOEBSEE/MSEE or equivalent; 3+ years in VLSI physical design on 5nm-3nm; strong P&R, timing, IR drop; scripting in Python/Perl/Tcl; experience with Synopsys and Cadence tools.
Synopsys ICC2, Synopsys DC, Synopsys PT, Synopsys STAR, Synopsys ICV, Cadence Genus, Cadence Innovus, Cadence Tempus, Python, Perl, Tcl, Make
2mo
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Senior Physical Design Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
8+ YOESenior Physical Design Engineer with 8+ years in ASIC/SoC physical design; Cadence Innovus expertise; floorplanning, CTS, routing; timing closure; scripting (Python/Tcl).
Cadence Innovus, Synopsys ICC2, Mentor Calibre, Tcl, Python, Verilog, SystemVerilog, UVM, VHDL
1mo
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Physical Design Engineer
Westford, Massachusetts, United States
$116k-$219k/yr OnsiteFull Time
3+ YOEBSEE/MSEE or equivalent; 3+ years VLSI physical design on 5/4/3nm; expertise in P&R, timing closure, power/clock distribution, verification; experience with Synopsys/Cadence EDA tools; Python/Perl/Tcl/Make scripting.
ICC2, DC, PT, STAR, ICV, Genus, Innovus, Tempus, Python, Perl, Tcl, Make
4d
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Senior Physical Design Engineer (200044384)
United States
OnsiteFull Time
Experienced engineer role focused on physical design of integrated circuits; senior-level experience expected.
4d
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Senior Physical Design Engineer
Raleigh or Mountain View or Austin
$120k-$235k/yr HybridFull Time
5+ YOEAdvanced degree in EE/CE/CS or equivalent with multi-year technical engineering experience; ability to pass Microsoft Cloud Background Check and satisfy export-control eligibility; experience in physical design implementation, timing, power, and verification.
4w
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Staff. Physical Design Engineer
San Diego, California, United States
$140k-$210k/yr OnsiteFull Time
2+ YOEBachelor's in science/engineering +2 years ASIC design experience (or Master's +1 or PhD). Requires ASIC design/verification skills, experience with architecture/design and scripting tools, and strong communication.
RTL to GDS Flow, Virtuoso
2w
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Silicon Physical Design Engineer
Sunnyvale, California, United States
$178k-$250k/yr OnsiteFull Time
8+ YOEBachelor's in CS/CE or equivalent, 8+ years physical design implementation for digital SoCs, experience with advanced nodes (3nm or below), EDA tools, timing/power/physical verification, and methodology development.
EDA tools, Python, Tcl
3mo
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Senior Physical Design Engineer
Chattanooga or Knoxville or Atlanta or Birmingham
HybridFull Time
8+ YOEBachelor's degree in Electrical Engineering; 8-12 years substation physical design experience; proficiency in 2D layout; strong communication.
AutoCAD, Inventor, Autodesk
1mo
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Principal Physical Design Engineer
Sunnyvale, California, United States
$174k-$353k/yr OnsiteFull Time
7+ YOEBS/MS in EE/CompEng, 7+ years ASIC physical design experience, strong expertise with Cadence Innovus and Synopsys Fusion Compiler, scripting in Tcl/Python/Linux shell, and physical signoff knowledge.
Cadence Innovus, Synopsys Fusion Compiler, Tcl, Python, Make, Linux shell, PrimeTime, StarRC, Voltus, RedHawk, Calibre, Git, Perforce
2mo
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Physical Design Engineer II (Silicon Engineering)
Bastrop or Irvine or Sunnyvale
$155k-$185k/yr OnsiteFull Time
3+ YOEBachelors in engineering; 3+ years RTL-to-GDSII physical design or flow development.
EDA tools, RTL-to-GDSII, Scripting (Python, TCL, Bash)
1mo
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Principal Physical Design Engineer
Sunnyvale, California, United States
$174k-$353k/yr OnsiteFull Time
7+ YOEBS/MS in EE/CE or related, 7+ years ASIC physical design/methodology experience, expertise with Cadence Innovus and/or Synopsys Fusion Compiler, strong scripting (Tcl, Python, Linux shell), and physical signoff knowledge.
Cadence Innovus, Synopsys Fusion Compiler, Tcl, Python, Make, Linux shell, PrimeTime, StarRC, Voltus, RedHawk, Calibre, Git, Perforce
2mo
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Principal Engineer – Physical Design
Chandler, Arizona, United States
OnsiteFull Time
10+ YOEBachelor’s or Masters in Electrical/Electronics Engineering; 10+ years in physical design; full-chip APR/physical implementation; TCL/Perl scripting; ICC/ICC2 or Innovus experience; 40nm/28nm tech; UPF and low power design; timing closure and sign-off tools.
ICC/ICC2, Innovus, TCL scripting, Perl scripting, Static Timing Analysis tools, Parasitic Extraction tools, Physical Verification tools, UPF and Low Power design tools
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