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211 physical design engineer jobs at 68 companies in Texas

3mo
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Physical Design Engineer
Austin or Fort Collins or Santa Clara
$100k-$500k/yr HybridFull Time
Tenstorrent
Tenstorrent: Designs and manufactures AI processors and RISC-V CPU solutions.
BS/MS/PhD in EE/ECE/CE/CS with experience in synthesis, PnR, timing closure; proficient with FusionCompiler, PrimeTime, RedHawk; scripting Tcl, Perl, Python; knowledge of low-power design; drive physical design from architecture to signoff.
FusionCompiler, PrimeTime, RedHawk, Tcl, Perl, Python
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2mo
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ASIC Physical Design Engineer
Maynard or Austin
$136k-$195k/yr HybridFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
5+ YOEBachelors in Engineering with 5+ years or Masters in Engineering with 3+ years in ASIC physical design; experience with floorplanning, place-and-route, STA, timing closure, DFT collaboration, scripting, and design flow optimization.
Cadence Innovus, Synopsys ICC2, Synopsys DC/FC, Synopsys Formality, Cadence LEC, Tempus, Python, TCL, Perl
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2w
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Senior Physical Design Engineer
Raleigh or Mountain View or Austin
$120k-$235k/yr HybridFull Time
Microsoft
MicrosoftNASDAQ: MSFT: Develops software, services, devices, and cloud computing solutions.
5+ YOEAdvanced degree in EE/CE/CS or equivalent with multi-year technical engineering experience; ability to pass Microsoft Cloud Background Check and satisfy export-control eligibility; experience in physical design implementation, timing, power, and verification.
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2w
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Physical Design Engineer- senior
Austin, Texas, United States
$116k-$173k/yr OnsiteFull Time
Qualcomm
QualcommNASDAQ: QCOM: Designs and manufactures semiconductors and wireless telecommunications products.
2+ YOEBachelor's in engineering or related plus 2+ years ASIC design/verification/validation/integration experience (or Master's/PhD alternatives), experience with architecture/design tools, scripting, and design verification methods.
RTL to GDS Flow, Virtuoso
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CPU Physical Design Engineer
Austin, Texas, United States
$106k-$200k/yr OnsiteFull Time
Intel
IntelNasdaq: INTC: Designs and manufactures microprocessors and semiconductor components.
2+ YOEBachelor’s or Master’s in Computer/Electrical Engineering with relevant experience; strong background in digital synthesis, physical design flows, and verification.
Synopsys, Cadence, Synthesis, Place and Route, Static Timing Analysis, DRC/LVS, TCL scripting
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3mo
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Physical Design Engineer II (Silicon Engineering)
Bastrop or Irvine or Sunnyvale
$155k-$185k/yr OnsiteFull Time
SpaceX
SpaceX: Designs and launches advanced rockets and satellite internet constellations.
3+ YOEBachelors in engineering; 3+ years RTL-to-GDSII physical design or flow development.
EDA tools, RTL-to-GDSII, Scripting (Python, TCL, Bash)
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2w
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SoC Physical Design Engineer, PnR
Austin, Texas, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
Seasoned technical leader in high-performance and low-power physical design for SoC; designs chip and IP physical architecture; collaborates with cross-functional teams.
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Senior Physical Design Engineer
Santa Clara or Austin
$168k-$311k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
8+ YOEBSEE (MSEE preferred) or equivalent, 8+ years VLSI physical design on 5/4/3nm, proven tapeout track record, expertise in power/performance/area, timing closure, P&R, RC extraction, and proficiency with Synopsys/Cadence/Mentor tools and scripting languages.
Synopsys ICC2, Synopsys DC, Synopsys PT, Synopsys STAR-RC, Synopsys ICV, Cadence Innovus, Cadence Tempus, Cadence SeaHawk, Mentor Graphics, Python, Perl, Tcl, Make, P&R
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1w
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Senior Staff Engineer, Physical Design (Floorplanning)
Austin, Texas, United States
$180k-$270k/yr OnsiteFull Time
Samsung Electronics
Samsung ElectronicsKorea Exchange: 005930: Develops and manufactures consumer electronics, semiconductors, and mobile devices.
11+ YOE7+ years hands-on physical-design experience; expertise in floorplanning, power-grid design, PNR flows, STA, physical verification; strong scripting and automation skills; leadership and mentoring experience.
FusionCompiler, Innovus, RedHawk, PrimeTime, Tempus, StarRC, Synopsys, Cadence, Python, Tcl, Shell, Perl
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2w
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Substation Physical Design Engineer
Pearland, Texas, United States
OnsiteFull Time
Kimley-Horn
Kimley-Horn: Provides professional engineering, planning, and design consulting services.
4+ YOE4+ years substation physical design experience; proficiency in AutoCAD, MicroStation, Inventor; experience with grounding/lightning studies; PE preferred or ability to obtain within 12 months.
AutoCAD, MicroStation, Inventor
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Staff Physical Design Engineer, HBM
Richardson, Texas, United States
OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Designs and manufactures semiconductor memory and data storage solutions.
7+ YOEBachelor's or Master’s in EE/CE or related,7+ years advanced-node physical design, tape-out experience, expertise in floorplanning, timing, power integrity, signoff, and PD flow automation.
Cadence Innovus, Synopsys ICC2, Fusion Compiler, PrimeTime, RedHawk, Calibre DRC/LVS, Tcl, Python
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2w
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Senior Physical Design Engineer
Austin, Texas, United States
$129k-$217k/yr OnsiteFull Time
MediaTek
MediaTekTaiwan Stock Exchange: 2454: Designs and develops system-on-chip solutions for electronic devices.
5+ YOEPerform APR and PV signoff for advanced-node CPU designs; strong scripting (Perl, Python, TCL, Make); 5+ years APR experience; knowledge of floorplanning, CTS, routing, signoff.
Perl, Python, TCL, Make
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1w
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Sr. Physical Design Engineer, Annapurna Labs
Austin or Cupertino
$159k-$248k/yr OnsiteFull Time
Amazon
AmazonNASDAQ: AMZN: Global online retail and cloud computing technology provider.
6+ YOE6+ years ASIC physical design experience, BS/MS in EE/CS, scripting with Python/Perl/Bash/PowerShell, EDA tool experience (Cadence/Mentor/Synopsys), timing/IR/physical verification sign-off expertise.
Python, Perl, Bash, PowerShell, Cadence, Mentor Graphics, Synopsys
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Senior ASIC Physical Design Engineer, Netlisting
Santa Clara or Austin
$136k-$265k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
3+ YOE5+ years (BS) or 3+ years (MS) experience in physical ASIC design, expertise in equivalence checking/FV, RTL/logic design, CDC/MTBF analysis, logic synthesis, STA and timing convergence, and scripting/programming skills.
Perl, TCL, Make, Python, Static Timing Analysis (STA)
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5d
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Physical Design Engineer - Block Level, Subsystem Implementation
Austin or San Jose
OnsiteFull Time
Etched
Etched: Designs specialized AI chips optimized for transformer architectures.
5+ YOE5+ years PDTools and RTL-to-GDSII flow experience; back-end physical design on advanced nodes; Cadence or Synopsys flow experience; sign-off tool proficiency; UPF low-power methodology; scripting in Tcl/Python/Perl.
PDTools, Cadence Innovus, Cadence Genus, Synopsys Fusion Compiler, PrimeTime, Tempus, Voltus, GDSII, UPF, Tcl, Python, Perl
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4w
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Austin Hiring Event - Senior Staff Physical Design Engineer
Austin, Texas, United States
$133k-$196k/yr OnsiteFull Time
Marvell Technology
Marvell TechnologyNASDAQ: MRVL: Developing semiconductor solutions for cloud, enterprise, and AI infrastructure.
5+ YOEBachelor's in CS/EE,5+ years physical design experience, RTL-to-GDS knowledge, scripting in Shell/Perl/TCL/Python, familiarity with static timing, EM/IR and verification tools.
Shell, Python, TCL, Perl, Verilog, Tempus, PrimeTime, Voltus, PrimeRail, Calibre, LEC, Formality, Cadence Innovus
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2mo
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Member of Technical Staff, Hardware, Physical Design Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
River AI
River AI: Building user-controlled, personalized AI with integrated local hardware.
5+ YOEBachelor's in EE/CE and 5+ years with advanced process nodes (7nm or below); hands-on experience with physical design, synthesis, P&R, STA, sign-off flows, UPF/CPF power intent, and scripting (Tcl/Python).
Innovus, Fusion Compiler, PrimeTime, RedHawk, Unified Power Format (UPF), Common Power Format (CPF), Tcl, Python
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CPU Core Physical Design Methodology Staff Engineer
Austin, Texas, United States
$156k-$268k/yr HybridFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
MS/PhD or equivalent experience in EE/CE, deep EDA and methodology expertise, mastery of physical design tools, advanced Tcl/Python/Perl scripting, signoff and multi-node implementation experience.
Synopsys Fusion Compiler/ICC2, Cadence Innovus, PrimeTime SI, RedHawk-SC, Voltus, Calibre, Tcl, Python, Perl
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1mo
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Senior Silicon Physical Design and Layout Engineer
Austin or San Diego or Renton or Seattle or California or Texas
$198k-$277k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOEB.S. in EE/CE or related, 7+ years ASIC physical design and layout experience, expertise in digital and analog layout, industry-standard EDA tools (Cadence, Synopsys, Mentor), timing closure, power analysis, and semiconductor process knowledge.
Cadence, Synopsys, Mentor
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2mo
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Sr Analog Physical Design Engineer | Kilby Labs
Dallas or Bengaluru
HybridFull Time
Texas Instruments
Texas InstrumentsNASDAQ: TXN: Designs and manufactures semiconductors and integrated circuits.
8+ YOEBachelor's degree in Electrical Engineering or related field with 8+ years of experience.
Cadence Allegro, TOTEM, Pcell Designer, LBC, CMOS, BiCMOS, GaN
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