49 rtl jobs at 12 companies in Carrollton, TX
1d
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RTL Design Engineer
Richardson, Texas, United States
HybridFull Time
Bachelor’s or master’s degree in engineering; experienced Verilog/SystemVerilog RTL designer with ASIC/SoC flows, synthesis, verification debug, EDA tools, and cross-functional IC development experience.
Verilog, SystemVerilog, ASIC, SoC, Electronic Design Automation (EDA), CDC, APR
3mo
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HBM SoC RTL Design Engineer
Folsom or Richardson
$146k-$297k/yr OnsiteFull Time
10+ YOEBachelor's or master's in EE/CE (required) with 10+ years' experience; proficiency in SystemVerilog/Verilog, SoC integration, RTL-to-GDS flow, EDA tools (Cadence/Synopsys/Siemens), and scripting (Python, TCL, Perl, shell).
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Python, TCL, Perl, Shell, Palladium, Veloce, Zebu
1w
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PrProServe Account Executive , NAMER RTL/CPG
Arlington or Chicago or Dallas
$170k-$230k/yr OnsiteFull Time
7+ YOE7+ years B2B/enterprise services sales experience, consultative selling to C-level, experience with large commercial deals, bachelor's in computer science/engineering or equivalent, strong analytics and negotiation skills.
AWS services, CRM systems
2mo
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Staff Wireless IC Digital Designer
Dallas, Texas, United States
OnsiteFull Time
8+ YOESenior level design engineer with 8-12 years in digital RF/wireless design, IC/SoC development, RTL, and verification.
RTL, Synthesis, STA, ATPG, RFIC, SoC, Digital design, FPGA design
3mo
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HBM Design Engineering Lead - MTS/SMTS/DMTS
Richardson, Texas, United States
OnsiteFull Time
Lead cross-functional HBM design programs; strong DRAM/HBM, CMOS design knowledge; RTL/Verilog experience; excellent communication and leadership.
Verilog, RTL, HSPICE, FastSpice, CMOS, DRAM
2w
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Director, Design Management
Richardson, Texas, United States
$191k-$332k/yr OnsiteFull Time
Proven track record delivering SoC programs, expertise across RTL/DV/DFT/Physical Design, program and cost modeling, SOW and contractor management, strong leadership and communication.
RTL, DV, DFT, Physical Design, EDA
2w
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Director, Design Management
Richardson, Texas, United States
$191k-$332k/yr OnsiteFull Time
Proven track record delivering complex SoC programs, expertise across RTL/DV/DFT/Physical Design, experience in cost/resource modeling, SOW and contractor management, customer-facing feasibility work, and leadership of global teams.
RTL, DV, DFT, Physical Design, EDA
1d
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Supply Chain Logistics Technician
Dallas, Texas, United States
OnsiteFull Time
3+ YOEHigh school diploma or GED, three years of logistics or supply chain experience preferred in healthcare, valid driver's license, MS Office, ERP, RFID and RTLS systems experience.
Microsoft Word, Microsoft Excel, ERP, RFID, RTLS
2w
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Senior Staff Digital Design Engineer
Plano, Texas, United States
HybridFull Time
5+ YOE5+ years in digital IC design with Verilog/SystemVerilog, RTL, synthesis, STA, verification, silicon debug, UVM and experience with industry EDA tools; B.Tech/M.Tech in electronics or related field.
Verilog/SystemVerilog, UVM, I²C, I3C, SPI, UART, Python, Tcl, Perl, Shell, Xcelium, Genus, SpyGlass, OneSpin/JasperGold, Innovus, PrimeTime/Tempus, DFT, ARM, AMBA (AXI/AHB/APB), Cadence Virtuoso, STA, LEC, Lint, Formal Verification
1mo
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Principal Engineer, Digital Design (IO Subsystem)
Allen, Texas, United States
OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
10+ YOEBachelor's in EE (Master's preferred), 10+ years digital IC/RTL design, expert SystemVerilog, Python, UVM, UPF/STA/timing signoff, DFT experience, and strong cross-functional collaboration.
SystemVerilog, Python, UVM, UPF, STA, DFT, AI/ML
2w
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Senior ASIC/FPGA Design Engineer
McKinney, Texas, United States
$87k-$165k/yr OnsiteFull Time
5+ YOEBachelor's in STEM,5+ years FPGA/ASIC design and RTL experience,experience with Xilinx/Altera and high-speed interfaces,Python/Perl/Shell scripting,ability to obtain U.S. government security clearance;U.S. citizenship required.
Xilinx, Altera, Python, Perl, Shell, System Verilog, UVM, MATLAB, PCI/PCIe, VPX, Gb Ethernet, Ienterlaken
2mo
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Principal Engineer DSP PHY Digital Design
Dallas, Texas, United States
HybridFull Time
10+ YOEB.S. +10 yrs or M.S. +7 yrs in EE/CE or related; strong digital communications/DSP fundamentals; experience with high-speed wireline DSP (FFE/DFE, CDR, FEC), RTL design/verification; C++, MATLAB proficiency.
C++, MATLAB, Python
1mo
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Digital IC Design Engineer
Dallas, Texas, United States
OnsiteFull Time
1+ YOEBachelor's in EE/CE or related; 1+ years digital IC design experience; proficiency in RTL (Verilog/SystemVerilog), functional verification, synthesis/static timing, low-power techniques; exposure to SPI/I2C/UART; scripting (Python, Tcl, Perl).
Verilog, SystemVerilog, Synopsys Design Compiler, Cadence Genus, Python, Tcl, Perl
1mo
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FPGA Implementation Specialist – 5G Radio Unit Digital Front End & High-PHY Solutions
Plano, Texas, United States
$105k-$195k/yr OnsiteFull Time
3+ YOEBachelor's in engineering, 3+ years FPGA development experience in telecom, strong RTL skills (VHDL/Verilog/SystemVerilog), experience with Vivado/Vitis and AMD Versal, DSP and FPGA implementation (synthesis, place-and-route, timing), lab validation and strong technical communication.
VHDL, Verilog, SystemVerilog, Vivado, Vitis, AMD Versal
2mo
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Full Stack Engineer (Delivery Toolkit)
Atlanta or Austin or Chicago or Dallas or Houston
$93k-$112k/yr HybridFull Time
2+ YOEBachelor's degree or equivalent; 2+ years building web or backend services; strong TypeScript, Node.js, FastAPI/Python, SQL/Postgres, testing, and practical AWS experience; familiarity with CI/CD, Docker, and IaC.
Svelte, SvelteKit, React, TypeScript, Node.js, Python, FastAPI, Zod, Pydantic v2, PostgreSQL, SQL, SQLAlchemy, Docker, Vitest, RTL, Jest, pytest, Playwright, OpenAPI, GitHub Actions, Cursor, GitHub Copilot, S3, RDS, Lambda, ECS, CloudWatch, IAM, API Gateway, SQS, SNS, EventBridge, ECR, Terraform, CloudFormation, CDK
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