118 rtl design engineer jobs at 34 companies in Taylor, TX
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VLSI RTL design engineer
Fort Collins or Austin
$106k-$183k/yr HybridFull Time
3+ YOEBS/MS in EE/CS/CSE with 3+ years hardware design experience; experience in Digital RTL design, Verilog HDL, SRAM/Coherent Cache/NOC, scripting; strong communication and problem-solving skills.
Verilog HDL
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Sr. RTL Design Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
$170k-$235k/yr OnsiteFull Time
5+ YOEBachelor’s in electrical/computer engineering or computer science; 5+ years of RTL implementation experience.
Verilog, SystemVerilog, Python, EDA tools, HDL simulators, HDL Lint
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CPU RTL Design Engineer
Austin or Phoenix
$142k-$269k/yr HybridFull Time
5+ YOEDegree in EE/CE/CS with significant experience (typical 5+ yrs); 7+ yrs RTL design with Verilog/V2K/SystemVerilog; low-power, CDC, static timing, UPF knowledge; scripting with TCL/Perl/Python; strong communication.
Verilog, V2K, System Verilog, TCL, Perl, Python, UPF, x86 assembly
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Senior Engineer, GPU RTL Design
Austin or San Jose
$124k-$208k/yr OnsiteFull Time
4+ YOEMaster’s in Electrical/Computer Engineering required for senior/staff; Senior requires 4+ years. Requires RTL design experience (Verilog/SystemVerilog), ASIC front-end flow familiarity, microarchitecture knowledge, and ability to access export-controlled information.
Verilog, SystemVerilog
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Staff RTL Design Engineer - CPU LS/PF/MMU
Santa Clara or Austin
$179k-$219k/yr OnsiteFull Time
3+ YOEBS/MS in CS/CE/EE or equivalent, 3+ years design experience, CPU RTL design experience, proficiency in Verilog/System Verilog/VHDL, strong software engineering (OOP, functional, TDD), verification skills (SVA, coverage).
Chisel, FIRRTL, Verilog, System Verilog, VHDL, Scala, Bluespec, RISC-V, Git/Github, Jira, Confluence, SVA
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Member of Technical Staff, Hardware, RTL Design Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE and 5+ years industry experience with advanced process nodes (7nm or below); strong RTL, synthesis, physical design, and timing tool experience; expertise in computer architecture and silicon delivery.
System Verilog, VCS, Verdi, Fusion Compiler, PrimeTime, C, C++, python, ISA assembly, PCIe, UCIe, HBM, DDR, AXI, CHI, Static Timing Analysis (STA)
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RTL Feasibility Engineer, AI/ML Processors
Austin, Texas, United States
$99k-$148k/yr OnsiteFull Time
Bachelor's in science/engineering required. Strong Python, Perl, Shell scripting; familiarity with SystemVerilog and RTL; experience with Git; experience in logic design, synthesis, timing and power analysis; strong communication and collaboration skills.
Python, Perl, Shell, SystemVerilog, RTL, Git, digital design simulator, design synthesis engine, power estimation engine
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Sr. Engineer, RTL Implementation
Austin or Santa Clara
$100k-$500k/yr HybridFull Time
Experienced in high-performance physical design; RTL coding (Verilog/VHDL); synthesis/place-and-run; CPU micro-architecture.
Verilog, VHDL, Synthesis tools, Place and Route tools
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RTL Design and Architect lead
San Jose or Austin
OnsiteFull Time
10+ YOE10+ years industry experience, Bachelor's/Master's in Electronics/Electrical Engineering, SOC project leadership, RTL design with VHDL/Verilog/SystemVerilog, strong digital design fundamentals, exposure to micro-processor integration and high-speed peripherals, Python familiarity.
VHDL, Verilog, SystemVerilog, Python, GDSII, DDR, PCIe, UCIe, Ethernet
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Sr. Staff SoC RTL Engineer
Austin, Texas, United States
OnsiteFull Time
8+ YOEBachelors in EE/CE (or higher),8+ years ASIC/SoC RTL design,strong Verilog/SystemVerilog skills,ARM/AMBA experience,front-end ASIC flow knowledge,experience with tapeout/silicon bring-up,and US work authorization.
Verilog, SystemVerilog, ARM, AMBA, AHB, APB, AXI, LINT, CDC, RDC, UPF, FPGA
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DDR Design Engineer
Austin, Texas, United States
OnsiteFull Time
Bachelor's in Electrical Engineering; RTL design with Verilog/SystemVerilog; timing constraints; DFT; DDR PHY knowledge.
Verilog, SystemVerilog, DFT, RTL design, Timing analysis, Unified Power Format
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
5+ YOE5+ years experience in digital/ASIC design, degree in EE/CE or equivalent, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), RTL implementation, and ASIC design flows.
NVLink, PCI-Express, Ethernet, UCIE, RTL
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Senior Design Engineer
Austin, Texas, United States
$162k-$219k/yr HybridFull Time
7+ YOEBachelors/Masters in CS/ECE,7+ years designing complex SoC/compute subsystems,strong digital hardware design and Verilog experience,PCIe/DDR/HBM/UCIe integration,RTL development and SoC design methodologies.
Verilog, Perl, Python, SystemVerilog, UVM, OVM, PCIe, DDR, HBM, UCIe, Ethernet
3w
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Lead FPGA Design Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBachelor's in EE/CE/CS,5+ years FPGA design experience, expertise in RTL, simulation/synthesis/timing, experience with AMD/Xilinx or Intel/Altera toolchains, familiarity with SPI,I2C,UART,Ethernet,PCIe,JESD and lab-based debug; leadership and cross-functional communication skills.
AMD/Xilinx, Intel/Altera, SPI, I2C, UART, Ethernet, PCIe, JESD, RTL, simulation, synthesis, timing analysis, digital oscilloscope, logic analyzer, function generator
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Principal RTL Methodology Architect (767547)
Austin, Texas, United States
HybridFull Time
10+ YOE10+ years experience with SystemVerilog/Verilog RTL design, RTL methodology and signoff (lint, CDC, static analysis), EDA simulators, IP reuse, UPF low-power flows, Python automation and CI/CD; BS/MS in EE/CS.
SystemVerilog, Verilog, SpyGlass, Synopsys VC SpyGlass, VC Lint, VCS, Xcelium, Questa, Python, CI/CD, UPF, CDC
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Senior Physical Design Engineer
Hillsboro or Redmond or Mountain View or Raleigh or Austin
$120k-$235k/yr HybridFull Time
5+ YOEExperience in SOC physical design, low-power methodology, RTL-to-GDS implementation, signoff (timing, physical verification, EMIR, formal equivalence), and collaboration across CAD, RTL, architecture, and power teams.
PrimePower
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R&D Engineer IC Design 4
Austin or San Jose
$122k-$195k/yr OnsiteFull Time
6+ YOEDesign and verify RTL/Verilog blocks for ASICs including synthesis, timing closure, formal verification, scripting, and RTL/gate-level power analysis. BS/MS in ECE and 6+ years experience.
Verilog, RTL, TCL, Perl, Synopsys Design Compiler, DC topo, Cadence RTL Compiler, Primetime, liberty (LIB), Synopsys Formality, Cadence Conformal, Spyglass, svn, git
2w
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FPGA Design Engineer III
Austin, Texas, United States
OnsiteFull Time
3+ YOE3+ years Verilog RTL FPGA design experience, Bachelor's degree in EE/CE, full FPGA design flow knowledge, proficiency with major FPGA tool suites, and experience with verification and timing closure.
Verilog, VHDL, SystemVerilog, Microchip PolarFire SoC, RISC-V, PCIe, Ethernet, SERDES, UVM, Libero SoC, Xilinx Vivado, Intel Quartus, logic analyzers, oscilloscopes, Linux
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ASIC Design Engineer - Hardware
Austin, Texas, United States
$116k-$219k/yr HybridFull Time
2+ YOEBS in EE/CE (or equivalent), 2+ years industry experience, strong Perl/Python scripting, RTL design (Verilog), SystemVerilog verification, SOC design/implementation and automation experience, CDC/performance debugging skills.
Perl, Python, Verilog, SystemVerilog, dc_shell, VCS, Debussy, GDB
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Principal PCIe Subsystem RTL lead
San Jose or Santa Clara or Austin or Seattle or Boston
HybridFull Time
10+ YOE10+ years digital IC design experience with 4+ years PCIe subsystem design/integration, strong SystemVerilog RTL skills, experience integrating PCIe controller/SerDes PHY, multi-clock-domain design, and ability to lead architectural work.
SystemVerilog, UVM, PCIe, CXL, SerDes