411 rtl engineer jobs at 79 companies in Atherton, CA
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RTL Engineer
Mountain View, California, United States
$250k-$375k/yr OnsiteFull Time
5+ YOE5+ years RTL/SoC design to silicon, expert Verilog/SystemVerilog, synthesis/timing/CDC/SDC awareness, microarchitecture skills, collaboration across DV/PD/DFT, and scripting in Python/Tcl.
SystemVerilog, Verilog, Python, Tcl, SDC, STA, UPF, HBM, PCIe, SerDes, RISC-V, FPGA
5d
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RTL integration Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOEBachelor's plus 12+ years experience; deep RTL, UVM/SystemVerilog, synthesis, timing, CDC/RDC, GLS, SDF simulations, NCSim/VCS, Palladium modeling, STA, and strong debugging and communication skills.
RTL, UVM, SystemVerilog, SDF, NCSim, VCS, Palladium
3w
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Senior RTL Engineer
Santa Clara, California, United States
$200k-$500k/yr OnsiteFull Time
8+ YOE8+ years RTL design experience for complex digital systems, expert Verilog/SystemVerilog, strong computer architecture and microarchitecture knowledge, tapeout ownership, memory and interconnect familiarity.
Verilog, SystemVerilog, AXI, CHI, ACE, LPDDR, DDR, HBM, FPGA
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CPU Systems RTL Engineer
Santa Clara, California, United States
$167k-$251k/yr OnsiteFull Time
5+ YOEMS in Computer/Electrical Engineering with 5+ years CPU RTL experience; strong microarchitecture knowledge; Verilog or VHDL experience; familiarity with timing, power, and simulators; scripting with Perl or Python.
Verilog, VHDL, Perl, Python
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Senior RTL Engineer, Interconnect Design
San Francisco, California, United States
$225k-$445k/yr HybridFull Time
Senior RTL engineer with deep Verilog/SystemVerilog expertise, SoC interconnect/NoC experience, protocol knowledge (AXI, APB, CXL, PCIe, Ethernet), RTL signoff flows, and track record from microarchitecture through tape-out.
Verilog, SystemVerilog, AXI, APB, CXL, PCIe, Ethernet, RDMA, RoCE, network-on-chip, NoC, FPGA, lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, design-for-test
4w
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RTL Design Engineer
San Jose, California, United States
HybridFull Time
Experience in RTL digital design and verification, Verilog/System Verilog, scripting (Perl/Tcl/Python), FPGA/SoC design concepts, and strong analytical and communication skills; Bachelor’s or Master’s in Computer or Electrical Engineering.
Verilog, System Verilog, Perl, Tcl, Python
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SoC RTL Design Engineer
San Jose or Bangalore
HybridFull Time
8+ YOEBS/MS in Electrical or Computer Engineering; 8+ years in digital IC design with chip infrastructure ownership (clocking, power management, reset/DFT) at block-lead or subsystem level; strong SystemVerilog and infrastructure RTL skills; experience with embedded microcontroller integration and security features.
SystemVerilog, RTL Design, Power Management, Clock Gating, Reset, DFT, BIST, Interrupt Controller, UART, JTAG, PCIe, UCIe
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
1d
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Senior RTL Design Engineer, TPU
Sunnyvale, California, United States
$163k-$236k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CE/CS or equivalent,8 years ASIC design experience,SystemVerilog/RTL coding,script experience (Tcl, Python, Perl),BLS/CPR? NO (ignore).
SystemVerilog, RTL, Tcl, Python, Perl
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FE RTL Infrastructure - CAD Engineer
Cupertino, California, United States
OnsiteFull Time
Design and build infrastructure for RTL/CAD to support next-generation high-performance, power-efficient processors and SoCs.
RTL, CAD, SoC
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Sr. Engineer, RTL Implementation
Austin or Santa Clara
$100k-$500k/yr HybridFull Time
Experienced in high-performance physical design; RTL coding (Verilog/VHDL); synthesis/place-and-run; CPU micro-architecture.
Verilog, VHDL, Synthesis tools, Place and Route tools
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Sr. RTL Design Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
$170k-$235k/yr OnsiteFull Time
5+ YOEBachelor’s in electrical/computer engineering or computer science; 5+ years of RTL implementation experience.
Verilog, SystemVerilog, Python, EDA tools, HDL simulators, HDL Lint
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Senior Engineer, RTL Design
San Jose, California, United States
$138k-$206k/yr OnsiteFull Time
5+ YOEBS with 5 years RTL development or MS with 3 years; PhD in Computer/Electrical Engineering; HDL/Verilog; FPGA; PCIe/CXL/NVMe; CAD tools.
Verilog, HDL, CAD tools, Synopsys, Mentor, Cadence, FPGA, PCIe, CXL, NVMe, AXI, DDR4/5, Ethernet
1mo
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Senior Engineer, GPU RTL Design
Austin or San Jose
$124k-$208k/yr OnsiteFull Time
4+ YOEMaster’s in Electrical/Computer Engineering required for senior/staff; Senior requires 4+ years. Requires RTL design experience (Verilog/SystemVerilog), ASIC front-end flow familiarity, microarchitecture knowledge, and ability to access export-controlled information.
Verilog, SystemVerilog
1d
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Senior Staff RTL Design Engineer - CPU Frontend
Santa Clara, California, United States
$206k-$251k/yr OnsiteFull Time
7+ YOEBS/MS in CS/CE/EE or equivalent,7+ years RTL/CPU microarchitecture experience,Proficient in Verilog/SystemVerilog/VHDL,software engineering skills,experience with CPU front-end blocks and verification.
Verilog, SystemVerilog, VHDL, Chisel, FIRRTL, Scala, Bluespec, Git, GitHub, Jira, Confluence, UVM
2w
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RTL Power Optimization Engineer – New College Grad 2026
Santa Clara, California, United States
$116k-$219k/yr OnsiteFull Time
MS or PhD in EE/CE (pursuing or recent); understanding of RTL low-power design, backend flows, power analysis tools; Python and ML experience; strong communication and RTL debugging skills.
PowerArtist, PrimeTime PX, Python, Verilog
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Member of Technical Staff, Hardware, RTL Design Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE and 5+ years industry experience with advanced process nodes (7nm or below); strong RTL, synthesis, physical design, and timing tool experience; expertise in computer architecture and silicon delivery.
System Verilog, VCS, Verdi, Fusion Compiler, PrimeTime, C, C++, python, ISA assembly, PCIe, UCIe, HBM, DDR, AXI, CHI, Static Timing Analysis (STA)
2w
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RTL Power Optimization Engineer – New College Grad 2026
Santa Clara, California, United States
$116k-$219k/yr OnsiteFull Time
MS or PhD in EE/CE or equivalent; understanding of RTL power optimization, low-power techniques, backend flows, experience with power analysis tools, and strong Python and communication skills.
PowerArtist, PrimeTime PX, Python, Verilog
1mo
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RTL Design and Architect lead
San Jose or Austin
OnsiteFull Time
10+ YOE10+ years industry experience, Bachelor's/Master's in Electronics/Electrical Engineering, SOC project leadership, RTL design with VHDL/Verilog/SystemVerilog, strong digital design fundamentals, exposure to micro-processor integration and high-speed peripherals, Python familiarity.
VHDL, Verilog, SystemVerilog, Python, GDSII, DDR, PCIe, UCIe, Ethernet
2mo
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Senior Principal Engineer, Micro-architecture and RTL
Santa Clara, California, United States
$182k-$273k/yr OnsiteFull Time
15+ YOEBachelor's in CS/EE with 15+ yrs; MS with 10-12 yrs; PhD with 8-10 yrs. SystemVerilog RTL, UVM, Ethernet, PCIe, CXL experience; leadership ability.
SystemVerilog, SystemVerilog Assertions, Universal Verification Methodology, RTL, PCIe, CXL, Ethernet
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