1mo
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Sr. RTL Design Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
$170k-$235k/yr OnsiteFull Time
5+ YOEBachelor’s in electrical/computer engineering or computer science; 5+ years of RTL implementation experience.
Verilog, SystemVerilog, Python, EDA tools, HDL simulators, HDL Lint
1d
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Senior Memory Controller RTL Design Engineer (200044189)
Redmond, Washington, United States
OnsiteFull Time
Experienced RTL design engineer to develop and verify memory controller logic for high-performance systems.
1d
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Senior Memory Controller RTL Design Engineer
Redmond or Mountain View or Raleigh or Austin or Hillsboro
$120k-$235k/yr HybridFull Time
1+ YOEDegree in EE/CE/CS or equivalent with 1–5+ years experience depending on degree, strong Verilog/SystemVerilog RTL design skills, DDR4/DDR5 controller experience preferred, scripting (Perl/Tcl/Python), familiarity with front-end verification and low-power/timing checks, ability to pass Microsoft security and export control screenings.
Verilog, System Verilog, Perl, Tcl, Python
2w
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Senior DFT Engineer
Seattle, Washington, United States
$170k-$250k/yr OnsiteFull Time
7+ YOEB.S./M.S. in EE or related, 7+ years DFT experience for complex SoCs, RTL DFT insertion, ATPG and pattern generation, MBIST/LBIST, scan architectures, low-power DFT, mixed-signal test methods, and strong RTL/gate/silicon debugging.
ATPG, MBIST, LBIST, RTL, IEEE 1149.x (JTAG)
2mo
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FPGA Engineer, Amazon LEO OISL
Redmond, Washington, United States
$117k-$160k/yr OnsiteFull Time
3+ YOEBachelor's degree in electrical engineering or equivalent; 3+ years FPGA/ASIC design and verification experience; Python scripting; experience with Xilinx/AMD or Altera FPGAs; SystemVerilog/UVM; RTL, timing, power optimization.
Xilinx/AMD FPGAs, Altera FPGAs, SystemVerilog, UVM, RTL, lint checks, CDC, RDC, HDL simulation, hardware-in-the-loop
2mo
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SLD FPGA Verification Engineer III - Lunar Permanence
Seattle or Space Coast
$131k-$183k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
5+ YOEBS/MS in Electrical or Computer Engineering; 5+ years FPGA/ASIC verification; RTL simulation tools; UVM; testbench development; DO-254 knowledge a plus.
QuestaSim, ModelSim, SystemVerilog, UVM, RTL, DO-254
2mo
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FPGA Engineer (WA, Seattle)
Seattle, Washington, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Designing and maintaining FPGA IP cores and FPGA-based systems for hardware security; RTL/C/C++, Python, VHDL/Verilog, Vivado; surveillance clearance eligibility; travel up to 10%.
RTL, C/C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Zynq, Agilex, AXI, ACE, Avalon, cocotb, pyuvm
3d
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Distinguished Engineer - Memory Architecture
Santa Clara or Austin or Redmond
$320k-$489k/yr OnsiteFull Time
18+ YOE18+ years industry/academic experience, advanced degree or equivalent experience in EE/CE/CS, expertise in memory architecture, RTL and ML-aware modeling, leadership and IP generation.
RTL, DRAM, SRAM, ML
1mo
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
3d
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Distinguished Engineer - Memory Architecture
Santa Clara or Austin or Redmond
$320k-$489k/yr OnsiteFull Time
18+ YOE18+ years of industry or academic experience in memory architecture, experience defining DRAM/SRAM interfaces, ML- and workload-aware modeling, RTL/microarchitecture expertise, and strong mentoring and leadership impact.
3w
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ASIC Engineering Technical Leader - CDC
San Jose or Austin or Seattle
$184k-$264k/yr HybridFull Time
8+ YOEExpertise in RTL development, CDC/RDC methodology, and static glitch analysis; 6–8+ years related experience (varies by degree); experience maintaining CDC/RDC flows and signing off constraints and waivers.
RTL, SDC, VCS, SystemVerilog Assertions (SVA)
3mo
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Staff Software Engineer - FPGA Logic Synthesis
San Jose or Austin or Seattle
HybridFull Time
Strong software engineering expertise in C++, experience in logic synthesis/EDA tools, multi-threaded systems, and collaboration across teams.
C++, EDA tools, Multi-threading, RTL synthesis, Logic synthesis, Compilers, Software engineering
4w
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Member of Technical Staff - Low Level & Kernels Capabilities
San Francisco or Toronto or Seattle
$200k-$350k/yr OnsiteFull Time
Experienced low-level systems engineer fluent in C/C++/CUDA and Python, kernel and kernel-optimization experience, hardware-aware coding, familiarity with LLMs, and ability to design robust, ungameable RL environments.
C, C++, CUDA, Python, assembly, cuBLAS, FFTW, OpenSSL, FPGA, RISC-V, SIMD, AVX, TPU, RTL, HDL, HLS, MLIR, LLVM, Mojo, Triton, gem5, Lean, Coq, SMT
10h
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Technical Architect
King County, Washington, United States
$95k-$192k/yr OnsiteFull Time
12+ YOE5+ Mgmt12+ years semiconductor experience with 5+ years leading SoC/full-chip implementation programs; RTL-to-GDSII expertise, advanced-node physical design, EDA tool experience, program leadership, and customer engagement.
Synopsys, Cadence, ICC2, Fusion Compiler, Innovus, Tempus, PrimeTime, RedHawk, Calibre, Voltus, StarRC
2mo
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CPU Performance Architect, Platform Architecture
Austin or Beaverton or Santa Clara or Seattle
OnsiteFull Time
20+ YOEBS degree; CPU architecture/micro-architecture; performance/power analysis; collaboration with design teams; scripting (Perl or Python); experience in CPU simulation environments.
C++, Python, Perl, CPU simulation, RTL, Modeling
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