2w
Save
Mark Applied
Hide
Principal ASIC Package Design Engineer
Seattle, Washington, United States
$200k-$280k/yr OnsiteFull Time
10+ YOEBachelor's in engineering, 10+ years ASIC package design experience with deep FC-BGA expertise; experience with SI/PI, thermal, substrate technologies, OSAT/vendor engagement, and EM/SI tools.
SIWave, HFSS, ADS
1mo
Save
Mark Applied
Hide
Sr Principal ASIC Design Engineer - Terawave
San Diego or California or Austin or Texas or Kent
$308k-$431k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
15+ YOEExperienced ASIC/SoC design and verification engineer with expertise in Verilog/SystemVerilog, DSP structures, ARM integration, interface protocols, FPGA flows, post-silicon bring-up; BS/MS in EE or related and 15+ years experience required.
Verilog, SystemVerilog, MATLAB, SystemC, C
3w
Save
Mark Applied
Hide
Manager, ASIC Sustaining engineer, Silicon Operations
Sunnyvale or Bellevue or San Diego
$175k-$272k/yr OnsiteFull Time
5+ YOE5+ Mgmt5+ years technical program management and people management experience; Bachelors in engineering/CS; experience with Unix/Linux, yield improvement, root cause and failure analysis, DOE, and partnering with process/equipment/design teams.
Unix, Linux, AWS, Agile
1w
Save
Mark Applied
Hide
Associate ASIC and/or FPGA Design and Verification Engineer
Tukwila, Washington, United States
$99k-$133k/yr OnsiteFull Time
2+ YOEUS-person requirement with ability to obtain U.S. Secret clearance; Bachelor's in engineering or related field; 2+ years ASIC/FPGA design or verification experience; SystemVerilog, hardware integration, and scripting experience.
SystemVerilog, System Verilog Assertions, UVM, HDL, LEC, CDC, linting, Palladium, JESD204C, PCIe, Ethernet, Make, Perl, Python, svn, cvs, git, Linux
3w
Save
Mark Applied
Hide
ASIC Engineering Technical Leader - CDC
San Jose or Austin or Seattle
$184k-$264k/yr HybridFull Time
8+ YOEExpertise in RTL development, CDC/RDC methodology, and static glitch analysis; 6–8+ years related experience (varies by degree); experience maintaining CDC/RDC flows and signing off constraints and waivers.
RTL, SDC, VCS, SystemVerilog Assertions (SVA)
1mo
Save
Mark Applied
Hide
FPGA/ASIC Design Engineer (Silicon Engineering)
Irvine or Redmond
$125k-$145k/yr OnsiteFull Time
1+ YOEBachelor’s in EE/CE/CS/Physics; 1+ years RTL design (SystemVerilog/Verilog/VHDL); strong Python/C/C++, and PCB/lab experience.
Verilog/SystemVerilog, VHDL, Python, C/C++, Bash, HDL simulators, Spyglass, Vivado, Quartus, AXI/APB/AHB protocols
1w
Save
Mark Applied
Hide
Associate ASIC and/or FPGA Design and Verification Engineer
Tukwila, Washington, United States
$99k-$133k/yr OnsiteFull Time
2+ YOEUS-person requirement for security clearance, BS in related field, experience with ASIC/FPGA design and verification using SystemVerilog, hardware integration/testing, and scripting; typically 2+ years.
SystemVerilog, System Verilog Assertions, PalladiumPro, HDL, JESD204C, PCIe, Ethernet, Make, Perl, Python, svn, cvs, git, Linux
1mo
Save
Mark Applied
Hide
Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
5+ YOE5+ years experience in digital/ASIC design, degree in EE/CE or equivalent, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), RTL implementation, and ASIC design flows.
NVLink, PCI-Express, Ethernet, UCIE, RTL
1mo
Save
Mark Applied
Hide
Principal Silicon Design Verification Engineer
Santa Clara or Mountain View or Hillsboro or Austin or Redmond
$143k-$275k/yr HybridFull Time
3+ YOEDegree in EE/CE/CS (or equivalent) with 3+ to 8+ years technical engineering experience depending on degree, experience in ASIC/SoC verification, UVM/SystemVerilog/Verilog and C proficiency, ability to pass Microsoft security screening.
UVM, C, Verilog, System Verilog
2mo
Save
Mark Applied
Hide
Senior Electrical Engineer, Radiation Effects & Avionics Reliability
Seattle, Washington, United States
$150k-$200k/yr OnsiteFull Time
4+ YOEBachelor’s in Electrical Engineering; 4+ years in radiation effects, avionics reliability, or high-reliability electronics; hands-on radiation testing; experience with FMEA/FMECA, FTA, derating; knowledge of FPGA/ASIC/power systems; able to translate test data into design decisions.
FPGAs, ASICs, Power electronics, COTS, Radiation test equipment, SPENVIS, OMERE, NOVICE
1mo
Save
Mark Applied
Hide
Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelors or Master's in EE/CE or equivalent experience, 5+ years relevant experience, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), delivering high-bandwidth datapath blocks, deep ASIC design flow knowledge.
NVLink Fusion, NVLink, PCI-Express, Ethernet, UCIE, RTL, SoC
1w
Save
Mark Applied
Hide
Cloud Acceleration Engineer – DPU & AI Infra
Seattle, Washington, United States
OnsiteFull Time
2+ YOE2+ years industry experience (PhD exception), proficiency in C/C++ and Linux systems, strong understanding of compute/network architecture and OS, experience in software-hardware co-design or high-performance networking or AI/ML systems.
C/C++, Linux, OVS, SR-IOV, eBPF, DPDK, FPGA, ASIC, GPU, CUDA, NCCL
2mo
Save
Mark Applied
Hide
Performance Modeling Lead
San Francisco or Seattle
$342k-$555k/yr HybridFull Time
2+ YOE2+ MgmtLead a small team to build performance modeling frameworks; analyze system-level tradeoffs across AI infrastructure; influence design decisions.
Performance modeling, Analytical modeling, Simulation, HPC, GPU, ASIC
Explore Jobs