16 rtl engineer jobs at 12 companies in Buckhall, VA
1mo
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Engineer
Fairfax, Virginia, United States
OnsiteFull Time
5+ YOE5+ years RTL FPGA design experience (VHDL/Verilog/SystemVerilog), experience implementing image/signal processing on FPGAs, Xilinx device experience, PCIe/CoaXPress/10GbE/DDR interfaces, MATLAB/Python/C++, Vitis HLS/AI, Linux driver experience, U.S. citizenship and ability to obtain clearance.
VHDL, Verilog, SystemVerilog, RTL, Xilinx Kintex, Xilinx Virtex, Xilinx Zynq, Xilinx Versal, Xilinx Alveo, PCIe, CoaXPress, 10GbE, DDR, Vitis HLS, Vitis AI, MATLAB, Python, C++, Linux
3mo
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FPGA Engineer (VA, Reston )
Reston, Virginia, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and FPGA-based systems for hardware security; RTL/C/C++, Python, VHDL/Verilog; simulation, verification, system integration; verification tools and toolchains.
RTL, C/C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Xilinx, Versal, Agilex, AXI, ACE, Avalon, IP core, cocotb, pyuvm
2mo
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FPGA Developer
Fairfax, Virginia, United States
OnsiteFull Time
5+ YOEU.S. citizen able to obtain security clearance. 5+ years RTL FPGA design (VHDL/Verilog/SystemVerilog), FPGA implementation of image/signal processing, experience with Xilinx devices, high-speed interfaces, MATLAB/Python/C++, Vitis HLS/AI, and Linux driver development.
VHDL, Verilog, SystemVerilog, RTL, FPGA, Kintex, Virtex, Xilinx Zynq, Xilinx Versal, Xilinx Alveo, PCIe, CoaXPress, 10GbE, DDR, MATLAB, Python, C++, Vitis HLS, Vitis AI, Linux
2w
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Electrical Engineer
Chantilly, Virginia, United States
OnsiteFull Time
Bachelor's degree or higher in electrical or computer engineering; experience with multilayer PCB design, schematic capture, layout, bring-up, testing, harsh environments, digital interfaces, EMI/EMC, and basic FPGA RTL or firmware.
PCB, FPGA RTL, I2C, CAN, UART, PCIe, SERDES, Ethernet, RF, SoC, microcontroller firmware
1w
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Principal Engineer - FPGA/ASIC Design
Reston or Washington, D.C. or Indianapolis or West Lafayette
$152k-$247k/yr HybridFull Time
5+ YOEBachelor's with 5+ years, master's with 3+ years, or PhD in electronics or computer engineering; U.S. citizenship required. FPGA/ASIC, RTL, VHDL/Verilog/SystemVerilog and verification experience required.
FPGA, ASIC, DO-254, VHDL, Verilog, SystemVerilog, TCL, Python, Shell, Windows, Linux, Git, SVN, Actel, Xilinx, MATLAB, Simulink, Cameo Systems Modeler, MagicDraw, SysML, ILA, JTAG, Microsoft Excel
1w
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Principal Engineer - FPGA/ASIC Design
Reston, Virginia, United States
$152k-$247k/yr HybridFull Time
5+ YOEBachelor's degree plus 5+ years, master's plus 3+ years, or PhD in electronics or computer engineering; U.S. citizenship required. FPGA/ASIC, RTL, verification, timing closure, and development tool experience required.
FPGA, ASIC, VHDL, Verilog, SystemVerilog, MATLAB, Simulink, Cameo Systems Modeler, MagicDraw, TCL, Python, Shell, Windows, Linux, Git, SVN, JTAG, ILA, DO-254, SysML, Actel, Xilinx, oscilloscopes, logic analyzers
2mo
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
2mo
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Firmware Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in CE/EE/CS, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado/SoC FPGAs, TCP/UDP/IP and serial protocols, Bash/Python scripting; U.S. Person required.
Verilog, SystemVerilog, Vivado Design Suite, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, Bash, Python, git, Bitbucket CI, Jenkins
1mo
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Sr. FPGA Engineer II
Chantilly, Virginia, United States
$143k-$215k/yr OnsiteFull Time
8+ YOEBachelor's in computer or electrical engineering with 8+ years experience, FPGA firmware design with VHDL, and ability to obtain/maintain U.S. government security clearance.
Xilinx, AMD Versal, VHDL, RTL, C, Python, MATLAB, DDR4, Aurora, AXI Stream, AXI Memory Mapped, Altium Designer
1mo
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Senior FPGA Engineer
Fairfax, Virginia, United States
$76k-$141k/yr OnsiteFull Time
4+ YOEBachelor's in EE/CE (or MS) and 6+ years (4+ with MS) experience in FPGA RTL design, timing closure, simulation/verification, Vivado/VHDL/SystemVerilog experience, lab bring‑up, and high‑speed interface integration.
Xilinx, Zynq Ultrascale+ MPSoC, Zynq Ultrascale+ RFSoC, Versal ACAP, Versal AI Engines, Vivado Design Suite, Vivado IP Integrator, Vivado HW Debugger, Chipscope, SmartDebug, Libero, Git, Modelsim, Questasim, Aldec, UVVM, UVM, OVM, VHDL, SystemVerilog, MATLAB, Simulink, Linux, C, C++
2mo
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Principal FPGA Engineer
Ashburn or Boston or Nashua or Tewksbury
$144k-$192k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CE, 10+ years FPGA hardware development, strong RTL skills (SystemVerilog/Verilog/VHDL), FPGA toolflow experience, lab test/debug proficiency, mentorship/leadership experience, US citizenship required; active security clearance preferred.
ModelSim, Questa, Xilinx ISE, Vivado, Vivado IP Integrator, SystemVerilog, Verilog, VHDL, Zynq MPSoC, Versal Adaptive SoC, UltraScale+, Microchip Libero SoC, Intel Quartus, ChipScope, TCL, oscilloscopes, logic analyzers
3w
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Senior ASIC Digital Design Engineer
Annapolis Junction or Boise or Salt Lake City or Bloomington or United States
$142k-$150k/yr RemoteFull Time
5+ YOEBachelor's in Electrical/Computer Engineering (or related) with 5+ years experience (Master's+3 acceptable), U.S. citizenship, ability to obtain DoD Secret clearance, 5–8+ years ASIC/FPGA RTL design experience, formal verification and verification-process experience, JIRA and Microsoft Office proficiency.
JIRA, Microsoft Office, STA
2mo
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Embedded FPGA Engineer
McLean, Virginia, United States
$87k-$198k/yr OnsiteFull Time
3+ YOE3+ years developing FPGA/SDR solutions; proficiency with Verilog/VHDL/SystemVerilog/HLS, Vitis/Vivado/Xilinx toolchains, Python/C++, MATLAB, Linux, Agile tools (Jira, Confluence); ability to obtain TS/SCI clearance; bachelor’s in EE or CE required.
Python, C++, MATLAB, Jira, Confluence, Verilog, VHDL, SystemVerilog, HLS, Vitis HLS, Vitis, Vivado, Tcl, Linux, UNIX, AXI-Stream, AXI-Lite, DMA, RTL, SDR, SOSA, VPX, GPU, Logic Analyzer, Oscilloscope, Spectrum Analyzer
1d
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Digital Signal Processing and FPGA Engineer
Laurel, Maryland, United States
$100k-$245k/yr OnsiteFull Time
3+ YOEBachelor's degree in a relevant engineering or computer science field, 3+ years of software development, VHDL or Verilog, FPGA and simulation tools, GitLab, and eligibility for Secret clearance with U.S. citizenship.
MATLAB, HDL, VHDL, Verilog, Xilinx Vivado, ModelSim, GitLab, CI/CD, FPGA, RTL, GPUs, SoCs, Xilinx Zynq
3w
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Lead ASIC Digital Design Engineer
Annapolis Junction or Boise or Salt Lake City or Bloomington or United States
$177k-$187k/yr RemoteFull Time
8+ YOEBachelor's in ECE or related plus 8+ years (or Master's plus 6+ years), strong RTL/ASIC/FPGA design experience, ASIC tape-out and timing closure experience, ability to obtain DoD Secret clearance, proficiency with JIRA and Microsoft Office.
JIRA, Microsoft Office
3mo
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Electrical Engineer FPGA/ASIC - Level 3/4 - Dulles
Dulles, Virginia, United States
$114k-$171k/yr OnsiteFull Time
5+ YOEBS with 5+ yrs or MS with 3+ yrs (Level 3) or PhD with 1+ yrs; SCI clearance; VHDL experience; FPGA design flow expertise; aerospace domain knowledge; leadership experience.
VHDL, RTL, Synthesis, Place and Route, Timing Analysis, Power Analysis, Vivado, QuestaSim, MATLAB, Simulink
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