6 rtl engineer jobs at 4 companies in Centreville, MD
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Senior ASIC Digital Design Engineer
Annapolis Junction or Boise or Salt Lake City or Bloomington or United States
$142k-$150k/yr RemoteFull Time
5+ YOEBachelor's in Electrical/Computer Engineering (or related) with 5+ years experience (Master's+3 acceptable), U.S. citizenship, ability to obtain DoD Secret clearance, 5–8+ years ASIC/FPGA RTL design experience, formal verification and verification-process experience, JIRA and Microsoft Office proficiency.
JIRA, Microsoft Office, STA
1mo
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FPGA Verification Engineer Level 3/4 - Linthicum
Linthicum, Maryland, United States
$120k-$179k/yr OnsiteFull Time
3+ YOEU.S. citizen required. FPGA verification experience with VUnit, HDL (SystemVerilog/Verilog/VHDL), testbench and coverage-driven verification, RTL debug, test plan development; ability to obtain DoD Secret/Top-Secret clearance.
VUnit, SystemVerilog, Verilog, VHDL, Synopsys, Mentor Graphics, SystemVerilog Assertions (SVA), Bash, Perl, Python, Tcl, Makefile, Xilinx, MicroChip, Kintex, Zynq ultrascale+, RTG4
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Digital Signal Processing and FPGA Engineer
Laurel, Maryland, United States
$100k-$245k/yr OnsiteFull Time
3+ YOEBachelor's degree in a relevant engineering or computer science field, 3+ years of software development, VHDL or Verilog, FPGA and simulation tools, GitLab, and eligibility for Secret clearance with U.S. citizenship.
MATLAB, HDL, VHDL, Verilog, Xilinx Vivado, ModelSim, GitLab, CI/CD, FPGA, RTL, GPUs, SoCs, Xilinx Zynq
1mo
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FPGA Verification Engineer Level 3/4 - Linthicum
Linthicum Heights, Maryland, United States
$120k-$179k/yr OnsiteFull Time
5+ YOEU.S. citizen with 3–8+ years FPGA/RTL verification experience, proficiency with VUnit and HDL (SystemVerilog/Verilog/VHDL), ability to obtain DoD Secret/Top-Secret clearance, and degree in EE/CE/CS or related field.
VUnit, SystemVerilog, Verilog, VHDL, Synopsys, Mentor Graphics, Bash, Perl, Python, Tcl, Makefile, Xilinx, MicroChip
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Lead ASIC Digital Design Engineer
Annapolis Junction or Boise or Salt Lake City or Bloomington or United States
$177k-$187k/yr RemoteFull Time
8+ YOEBachelor's in ECE or related plus 8+ years (or Master's plus 6+ years), strong RTL/ASIC/FPGA design experience, ASIC tape-out and timing closure experience, ability to obtain DoD Secret clearance, proficiency with JIRA and Microsoft Office.
JIRA, Microsoft Office
2w
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Sr. FPGA Developer (Hybrid- Aberdeen Proving Ground, Maryland)
Aberdeen Proving Ground or Middletown
$150k-$175k/yr HybridFull Time
10+ YOEBachelor's in EE/CE,10+ years FPGA design experience with Xilinx Vivado, Verilog/VHDL, RFSoC/Versal platforms, RTL-to-hardware validation, AXI interfaces, and eligibility for DoD Secret clearance.
Xilinx Vivado, Verilog, VHDL, Siemens Questa, Vivado Simulator, Xilinx Zynq UltraScale+ RFSoC, Zynq UltraScale+ MPSoC, Versal, Versal ACAP, ADRV9009, AD9081, ADRV9009-ZU11EG, AXI-Lite, AXI-Stream, JESD204B, JESD204C, JTAG, Integrated Logic Analyzer (ILA), VIO, Ethernet, PCIe, Tcl, Python