2w
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Fall 2026 Co-Op - Digital Design Engineer
Greensboro, North Carolina, United States
HybridInternship
Pursuing MS or PhD in Electrical Engineering or related field; strong DSP knowledge; proficiency in Verilog, Synopsys flows, and Matlab; experience with RTL design, simulation, and verification.
Verilog, Synopsys, Matlab
4d
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Staff FPGA Systems Development Engineer
Durham or Wilmington
$125k-$181k/yr OnsiteFull Time
Bachelor's in electrical/computer engineering, strong FPGA/SoC and RTL experience, familiarity with Intel/Altera or AMD-Xilinx, proficiency in C/C++, Python, TCL, strong communication and coordination skills.
Intel-Altera, AMD-Xilinx, C, C++, Python, TCL, Electronic Test Equipment
1w
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Senior ASIC Design Engineer
Santa Clara or Durham
$168k-$311k/yr OnsiteFull Time
8+ YOEMasters in EE/CE (or equivalent),8+ years ASIC design experience,micro-architecture and RTL in Verilog,ASIC flow knowledge,EMR not applicable.
Verilog, Python, Perl, C, C++
1mo
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Senior Physical Design and Timing Engineer
Santa Clara or Austin or Hillsboro or Durham
$136k-$265k/yr HybridFull Time
3+ YOEBS in Electrical or Computer Engineering with 5+ years or MS with 3+ years; strong static timing analysis, synthesis, physical design, timing convergence, RTL/logic understanding; proficiency with Perl, Tcl, Make, Python.
Perl, Tcl, Make, Python
1mo
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FPGA Systems Development Engineer
Copenhagen or Durham
OnsiteFull Time
Bachelor's in electrical/computer engineering, hands-on FPGA/SoC programming experience, strong communication and problem-solving, ability to work on multiple projects and deliver high-quality results.
FPGA, SoC, HDL, IP, RTL, Intel-Altera, AMD-Xilinx, C/C++, Python, TCL, ATE
2mo
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Senior ASIC Power Engineer
Santa Clara or Austin or Durham or United States
$136k-$265k/yr OnsiteFull Time
5+ YOEBS or MS in electrical engineering or computer science; 5+ years in high-performance processor designs; SystemVerilog or HDL; VLSI/physical design; strong communication; computer architecture.
SystemVerilog, HDL, VLSI, RTL
2mo
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Staff Engineer - Digital ASIC and Signal Processing Chip Architect/Systems Engineer
Durham, North Carolina, United States
$131k-$190k/yr OnsiteFull Time
10+ YOE10+ years of experience, including 5 years in digital IC design; expertise in digital signal processing, RTL design, digital architecture; firmware and embedded software; radio architecture; microprocessor subsystems; experience across hardware-software co-design.
SystemVerilog, MATLAB, Python, DSP cores
1mo
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Senior ASIC Design Engineer - Agentic AI
Santa Clara or Austin or Durham
$168k-$311k/yr OnsiteFull Time
8+ YOEMaster's/PhD or equivalent experience, 8+ years experience, micro-architecture and RTL (Verilog) expertise, ASIC design flow knowledge, Python prototyping, experience with LLM fine-tuning, RAG pipelines, and vector databases.
Verilog, Python, RAG pipelines, vector databases, large language models