3mo
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Mark Applied
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Sr. RTL Engineer
Orlando, Florida, United States
OnsiteFull Time
5+ YOESenior FPGA/RTL engineer with SystemVerilog, FPGA design, modeling, simulation, verification, and test; knowledge of DSP, firmware, and hardware integration.
SystemVerilog, Verilog, Python, FPGA design, HDL Synthesis, VCS, Synplify, Git, Jira
3mo
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Mark Applied
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Staff RTL Engineer
Orlando, Florida, United States
OnsiteFull Time
7+ YOEStaff RTL Engineer with FPGA/RTL design, SystemVerilog, modelling, simulation, verification, integration and test; derive FPGA requirements from system; perform RTL design and testing.
SystemVerilog, Verilog, Python, FPGA design tools, HDL synthesis, VCS, Synplicity