182 rtl engineer jobs at 42 companies in Luling, TX
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RTL Power Analysis Engineer
Austin, Texas, United States
$127k-$217k/yr HybridFull Time
Bachelor or Masters in Electrical Engineering or Computer Science; strong RTL power reduction experience; power analysis tools proficiency.
Ptpx, Power Artist, RTL design, Python
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RTL Feasibility Engineer, AI/ML Processors
Austin, Texas, United States
$99k-$148k/yr OnsiteFull Time
Bachelor's in science/engineering required. Strong Python, Perl, Shell scripting; familiarity with SystemVerilog and RTL; experience with Git; experience in logic design, synthesis, timing and power analysis; strong communication and collaboration skills.
Python, Perl, Shell, SystemVerilog, RTL, Git, digital design simulator, design synthesis engine, power estimation engine
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Sr. Engineer, RTL Implementation
Austin or Santa Clara
$100k-$500k/yr HybridFull Time
Experienced in high-performance physical design; RTL coding (Verilog/VHDL); synthesis/place-and-run; CPU micro-architecture.
Verilog, VHDL, Synthesis tools, Place and Route tools
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Sr. RTL Design Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
$170k-$235k/yr OnsiteFull Time
5+ YOEBachelor’s in electrical/computer engineering or computer science; 5+ years of RTL implementation experience.
Verilog, SystemVerilog, Python, EDA tools, HDL simulators, HDL Lint
2w
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Sr. Staff SoC RTL Engineer
Austin, Texas, United States
OnsiteFull Time
8+ YOEBachelors in EE/CE (or higher),8+ years ASIC/SoC RTL design,strong Verilog/SystemVerilog skills,ARM/AMBA experience,front-end ASIC flow knowledge,experience with tapeout/silicon bring-up,and US work authorization.
Verilog, SystemVerilog, ARM, AMBA, AHB, APB, AXI, LINT, CDC, RDC, UPF, FPGA
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CPU RTL Design Engineer
Austin or Phoenix
$142k-$269k/yr HybridFull Time
5+ YOEDegree in EE/CE/CS with significant experience (typical 5+ yrs); 7+ yrs RTL design with Verilog/V2K/SystemVerilog; low-power, CDC, static timing, UPF knowledge; scripting with TCL/Perl/Python; strong communication.
Verilog, V2K, System Verilog, TCL, Perl, Python, UPF, x86 assembly
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Senior Engineer, GPU RTL Design
Austin or San Jose
$124k-$208k/yr OnsiteFull Time
4+ YOEMaster’s in Electrical/Computer Engineering required for senior/staff; Senior requires 4+ years. Requires RTL design experience (Verilog/SystemVerilog), ASIC front-end flow familiarity, microarchitecture knowledge, and ability to access export-controlled information.
Verilog, SystemVerilog
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Staff RTL Design Engineer - CPU LS/PF/MMU
Santa Clara or Austin
$179k-$219k/yr OnsiteFull Time
3+ YOEBS/MS in CS/CE/EE or equivalent, 3+ years design experience, CPU RTL design experience, proficiency in Verilog/System Verilog/VHDL, strong software engineering (OOP, functional, TDD), verification skills (SVA, coverage).
Chisel, FIRRTL, Verilog, System Verilog, VHDL, Scala, Bluespec, RISC-V, Git/Github, Jira, Confluence, SVA
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Member of Technical Staff, Hardware, RTL Design Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE and 5+ years industry experience with advanced process nodes (7nm or below); strong RTL, synthesis, physical design, and timing tool experience; expertise in computer architecture and silicon delivery.
System Verilog, VCS, Verdi, Fusion Compiler, PrimeTime, C, C++, python, ISA assembly, PCIe, UCIe, HBM, DDR, AXI, CHI, Static Timing Analysis (STA)
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RTL Design and Architect lead
San Jose or Austin
OnsiteFull Time
10+ YOE10+ years industry experience, Bachelor's/Master's in Electronics/Electrical Engineering, SOC project leadership, RTL design with VHDL/Verilog/SystemVerilog, strong digital design fundamentals, exposure to micro-processor integration and high-speed peripherals, Python familiarity.
VHDL, Verilog, SystemVerilog, Python, GDSII, DDR, PCIe, UCIe, Ethernet
3w
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Principal PCIe Subsystem RTL lead
San Jose or Santa Clara or Austin or Seattle or Boston
HybridFull Time
10+ YOE10+ years digital IC design experience with 4+ years PCIe subsystem design/integration, strong SystemVerilog RTL skills, experience integrating PCIe controller/SerDes PHY, multi-clock-domain design, and ability to lead architectural work.
SystemVerilog, UVM, PCIe, CXL, SerDes
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FE RTL Infrastructure - CAD Engineer
Austin, Texas, United States
OnsiteFull Time
Design and manufacture next-generation, high-performance, power-efficient processors and SoCs as part of a silicon technologies team; craft and build enabling technology for Apple devices.
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Software R&D Engineer, RTL Optimization Tools
Santa Clara or Austin
$136k-$219k/yr HybridFull Time
3+ YOEMS/PhD in EE or CS (or equivalent experience), 3+ years CAD/VLSI experience, strong C++ and algorithm development, familiarity with RTL (Verilog/SystemVerilog), EDA techniques, and ML techniques for analysis and optimization.
C++, Verilog, SystemVerilog, Verific, Espresso, SAT solvers, LLMs, GNNs, GANs
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Principal DFT Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years DFT implementation and verification experience including scan architectures, JTAG, memory MBIST, ATPG; Verilog/VHDL RTL knowledge; ability to handle RTL DFT changes, analyze ATPG/DRC reports, and support test pattern bring-up.
RTL, MBIST, ATPG, JTAG, TAP, ATE, Verilog, VHDL, SDF
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Security IP Design Engineer
Austin, Texas, United States
$162k-$219k/yr HybridFull Time
Bachelor's or graduate degree in computer science or electrical/computer engineering, with advanced Verilog RTL, security hardware, SoC architecture, EDA, scripting, and SystemVerilog experience.
Verilog, RTL, EDA, AXI, AHB, Perl, Python, TCL, SystemVerilog, UVM, OVM, Portable Stimulus, UPF, CDC, RDC, LINT
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DSP Algorithm Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years developing modem algorithms (clock recovery, equalization, phase/track), fixed-point MATLAB and C programming, lab debugging/tuning, understanding MATLAB-to-RTL HW constraints; BSc in Electrical Engineering.
MATLAB, C, RTL
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Senior Firmware Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBS/MS in EE or Computer Engineering required; 5+ years firmware verification experience in pre-silicon; SystemVerilog, C, Python/Perl skills; familiarity with RTL, emulation, and lab test equipment.
SystemVerilog, UVM, C, Python, Perl, RTL, FPGA, QEMU, SimVision, Verdi, oscilloscopes, power supplies, logic analyzers
1w
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ASIC Engineer, Design
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's degree or equivalent,6+ years hardware design experience for production silicon,expertise in microarchitecture,RTL and SoC integration,strong communication and collaboration skills.
RTL, Synthesis, Timing Closure, Formal Verification Methodology, SoC, EMR
3mo
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FPGA Engineer (TX, Austin)
Austin, Texas, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and systems; experience with RTL, C/C++, Python, VHDL/Verilog; FPGA toolchains; security clearance.
RTL, C/C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Zynq, Versal, Altera, Stratix, AXI, ACE, Avalon, cocotb, pyuvm
1w
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R&D Engineer IC Design 4
Austin or San Jose
$122k-$195k/yr OnsiteFull Time
6+ YOEDesign and verify RTL/Verilog blocks for ASICs including synthesis, timing closure, formal verification, scripting, and RTL/gate-level power analysis. BS/MS in ECE and 6+ years experience.
Verilog, RTL, TCL, Perl, Synopsys Design Compiler, DC topo, Cadence RTL Compiler, Primetime, liberty (LIB), Synopsys Formality, Cadence Conformal, Spyglass, svn, git
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