28 rtl engineer jobs at 11 companies in Maryvale, AZ
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CPU RTL Design Engineer
Austin or Phoenix
$142k-$269k/yr HybridFull Time
5+ YOEDegree in EE/CE/CS with significant experience (typical 5+ yrs); 7+ yrs RTL design with Verilog/V2K/SystemVerilog; low-power, CDC, static timing, UPF knowledge; scripting with TCL/Perl/Python; strong communication.
Verilog, V2K, System Verilog, TCL, Perl, Python, UPF, x86 assembly
1w
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Hardware Design Engineer
Tempe or San Jose or San Francisco or New York City
$133k-$210k/yr OnsiteFull Time
4+ YOEBachelor's degree or equivalent in electrical or computer engineering, 4+ years in high-speed digital board design and FPGA/RTL development, US citizenship, Secret clearance eligibility, and up to 10% travel.
SystemVerilog, Verilog, VHDL, AMD Vivado, Intel Quartus, Synopsys Synplify, Mentor Xpedition, Cadence, Altium, HyperLynx, Python, TCL, Perl, ModelSim, Questa, Git, Claude Code, Copilot, DDR4, SERDES, UART, I2C, SPI, LVDS, FPGA, RTL, SoC, ADC, DAC, CI/CD, AI
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Principal Engineer Electrical
Gilbert, Arizona, United States
$98k-$148k/yr OnsiteFull Time
5+ YOEBachelor's degree in a STEM discipline plus 5 years of experience, or a relevant advanced degree with less experience. Requires RTL FPGA design, simulation, synthesis, place-and-route, and aerospace experience.
FPGA, ASIC, HDL, RTL, Electronic Design Automation (EDA) Tools, Xilinx ISE, Vivado, Mentor Graphics ModelSim, QuestaSim, Synplify, System Verilog, Universal Verification Methodology (UVM), Signal Generators, Logic Analyzers, Digital Oscilloscopes, Embedded FPGA Debugging tools
1w
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Principal Digital Engineer (DFT Design)
Chandler or Bangalore
HybridFull Time
12+ YOEBSEE required; MSEE preferred. Requires 12+ years with a master's or 15+ with a bachelor's in digital design and DFT, eight tapeouts, scan, ATPG, RTL, synthesis, and industry-standard DFT tools.
ATPG, Verilog, SystemVerilog, Synopsys, Cadence, Mentor, Siemens, Tetramax, RTL, LINT, CDC, P&R
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Principal Engineer- Design (FPGA)
Chandler, Arizona, United States
OnsiteFull Time
10+ YOE10+ years in FPGA or digital design; expertise in RTL, Verilog/SystemVerilog, simulation, synthesis, timing, implementation, multi-clock systems, board bring-up, lab debugging, and technical documentation.
Verilog, SystemVerilog, QuestaSim, ModelSim, AMD/Xilinx Vivado, TCL, Python, Perl, Linux, C++, RUST, Perforce, Git, DesignSync, FPGA, RTL
2d
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Senior Digital Design Engineer
Vancouver or Chandler or San Francisco
$150k-$200k/yr HybridFull Time
6+ YOEBachelor's or master's degree in electrical or computer engineering, 6+ years of digital IC design experience, and hands-on Verilog or SystemVerilog RTL development for complex SoCs or ASICs.
Verilog, SystemVerilog, Synopsys, Cadence, SDC, UPF, CPF
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Staff Engineer, Design Verification Engineering
Chandler, Arizona, United States
$172k-$199k/yr HybridFull Time
4+ YOEMaster's degree in Electrical Engineering, Materials Engineering, or Physics with 4 years in design verification; or Bachelor's with 6 years; strong SystemVerilog/UVM skills; Verilog-RTL, mixed-signal verification; Xcelium/VCS; scripting (Perl/Python/C).
SystemVerilog, UVM, Verilog-AMS, Cadence AMS, Xcelium, VCS, Perl, Python, C
1mo
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Senior DfT Engineer
Chandler, Arizona, United States
HybridFull Time
3+ YOEMaster's (MSEE) in relevant fields, 3+ years DfT/digital design experience, strong RTL coding and verification skills, Verilog/SystemVerilog proficiency, problem solving and communication skills.
Verilog, SystemVerilog
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FPGA Engineer (AZ, Phoenix)
Phoenix, Arizona, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and hardware security systems; RTL, C/C++, Python, VHDL/Verilog; FPGA tools; security clearance.
VHDL, Verilog, SystemVerilog, Python, C, C++, Tcl, Vivado, Questa, GHDL, Quartus Prime, Xilinx, Versal, AcE, AXI, Avalon
3d
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Principal Engineer Electrical
Gilbert, Arizona, United States
$98k-$148k/yr OnsiteFull Time
5+ YOEBachelor’s degree in STEM with 5 years’ experience, master’s with 3 years, or PhD with 1 year. Requires aerospace RTL design, FPGA design flow, simulation, synthesis, place-and-route, and timing analysis experience.
Electronic Design Automation (EDA) Tools, Xilinx ISE, Xilinx Vivado, Mentor Graphics ModelSim, Mentor Graphics QuestaSim, Synplify, SystemVerilog, Universal Verification Methodology (UVM), Signal Generators, Logic Analyzers, Digital Oscilloscopes, Embedded FPGA Debugging tools
3w
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Senior Design Verification Engineer
Tempe or Independence
$156k-$291k/yr RemoteFull Time
8+ YOE8+ years design verification experience with UVM, SystemVerilog, RTL verification for FPGA/ASIC, Bachelor's in EE/CE, US citizenship, ability to obtain Secret clearance, familiarity with Questa/Xcelium/VCS and AI verification tools.
Universal Verification Methodology (UVM), SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
2w
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Systems and Test Integration Engineer - FPGA Integration & Verification
Scottsdale, Arizona, United States
$91k-$101k/yr OnsiteFull Time
2+ YOEBachelor's in systems/engineering/math plus 2+ years (or Master's plus 6 months), TS/SCI clearance obtainable, FPGA design and hardware bring-up experience, RTL (SystemVerilog/VHDL), scripting (Python,Tcl), Linux and Git proficiency.
SystemVerilog, VHDL, Xilinx/AMD Vivado, Lattice Diamond, Radiant, Python, Tcl, Git, GitLab CI, RHEL, Ubuntu, Linux shell scripts, JTAG, oscilloscope, protocol analyzer
1w
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Senior Principal Mixed Signal Design Engineer (Hybrid)
Goleta or Phoenix
$146k-$277k/yr HybridFull Time
10+ YOESTEM degree with 10+ years of relevant experience or advanced degree with 7+ years; requires mixed-signal ASIC/ROIC, CMOS IC design, semiconductor processing, simulation, layout, testing, and team leadership experience.
Cadence, Mentor Graphics, MATLAB, Python, UNIX, SystemVerilog, Verilog-AMS, Conformal, Innovus, RTL
3w
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Hardware Designer
Phoenix or United States
RemoteFull Time
5+ YOE5+ years electronics design experience, Bachelors in Electrical/Computer Engineering, high-speed PCB and system design expertise, familiarity with FPGA and signal integrity, bench bring-up and test experience.
LTSpice, OrCAD Capture CIS, Cadence CIS, Cadence Allegro, Verilog, RTL, HLS, optical test set, signal analyzer, oscilloscope, VNA, signal generator
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