19 rtl engineer jobs at 15 companies in Mercerville, NJ
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Hardware Engineer, RTL/PD
New York City or London or Zurich or Palo Alto or Copenhagen or Seoul
$200k-$285k/yr OnsiteFull Time
Production SystemVerilog RTL experience, synthesis and place-and-route through tapeout, experience with backend flows and timing closure, familiarity with formal methods and post-silicon bring-up; multiple tapeouts preferred.
SystemVerilog, RISC-V, GDSII, CTS, DFT, LVS, DRC
2mo
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Senior FPGA Engineer
Chicago or New York City or London
$225k-$325k/yr OnsiteFull Time
3+ YOEBachelor's in Computer or Electrical Engineering, 3+ years FPGA/hardware engineering experience, RTL/Verilog expertise, FPGA design flow experience, knowledge of TCP/IP, strong autonomous and problem-solving skills.
Verilog, System Verilog, RTL, XILINX, ALTERA, TCP/IP, synthesis, place & route, static timing analysis
1w
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Hardware Design Engineer
Tempe or San Jose or San Francisco or New York City
$133k-$210k/yr OnsiteFull Time
4+ YOEBachelor's degree or equivalent in electrical or computer engineering, 4+ years in high-speed digital board design and FPGA/RTL development, US citizenship, Secret clearance eligibility, and up to 10% travel.
SystemVerilog, Verilog, VHDL, AMD Vivado, Intel Quartus, Synopsys Synplify, Mentor Xpedition, Cadence, Altium, HyperLynx, Python, TCL, Perl, ModelSim, Questa, Git, Claude Code, Copilot, DDR4, SERDES, UART, I2C, SPI, LVDS, FPGA, RTL, SoC, ADC, DAC, CI/CD, AI
2mo
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Senior FPGA Engineer
Chicago or New York City or London or United States or Canada or Europe or Asia
OnsiteFull Time
3+ YOEBachelor's in Computer/Electrical Engineering, 3+ years FPGA/hardware experience, Verilog/System Verilog and RTL skills, FPGA design flow (synthesis, place & route, static timing), SoC and TCP/IP knowledge, lab debugging, EM/board characterization.
Verilog, System Verilog, RTL, TCP/IP, XILINX, ALTERA
1mo
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FPGA Engineer - Control Systems
Princeton, New Jersey, United States
$150k-$235k/yr OnsiteFull Time
Experienced in FPGA/ASIC digital logic design and verification, RTL and low-latency firmware for multi-domain clock systems; familiarity with Xilinx/AMD RFSoC platforms preferred.
RTL, FPGAs, ASICs, Xilinx, AMD, RFSoC
2mo
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Staff Engineer, Digital ASIC Design (CONTRACT)
Burlington or New York
HybridContract
8+ YOEBS/MS/PhD in EE/CE; 8+ yrs in digital IC/ASIC/SoC; RTL ownership; SystemVerilog/Verilog; high-throughput datapaths; silicon constraints; SV/UVM; Python/cocotb; post-silicon bring-up.
SystemVerilog/Verilog, UVM, Python, cocotb, RTL, RTL verification, Fixed-point modeling
1mo
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Customer Projects Hardware Engineer – Aerospace, Defense & Government (ADG)
Hazlet or Portsmouth
$135k-$195k/yr OnsiteFull Time
6+ YOEBachelor's in EE/CE or related, 6+ years hardware design/RTL/board-level experience, FPGA systems familiarity, high-speed interface knowledge (DDR, PCIe, Ethernet), lab debugging experience, eligible for U.S. security clearance.
oscilloscope, logic analyzer, RTL, PCIe, Ethernet, DDR
2w
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ML ASIC Design Engineer
Mountain View or New York City
$175k-$215k/yr HybridFull Time
5+ YOEBS in Computer Engineering or equivalent experience; 5+ years with SystemVerilog, ASIC RTL design, and microarchitecture; 3+ years designing high-performance CPU, GPU, or NPU cores; Python or C++.
SystemVerilog, Python, C++, Chisel, Scala
1mo
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Engineer II-Design
Allentown, Pennsylvania, United States
OnsiteFull Time
2+ YOE2+ years RTL design experience for ASIC, Bachelor’s in EE/CE/CS required, SystemVerilog and scripting (TCL/Perl/Python), Linux, static timing and simulation experience, US citizenship or permanent residency required.
SystemVerilog, Verilog, TCL, Perl, Python, LINUX, FPGA
2mo
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Senior Engineer, Digital Design Engineering
Somerset, New Jersey, United States
$127k-$175k/yr HybridFull Time
2+ YOEMaster’s degree in Electrical/Electronic/Computer Engineering or related field; 2+ years in digital design/mixed-signal verification; experience with RTL, Verilog/SystemVerilog, and ASIC/FPGA design flows.
Verilog, SystemVerilog, Cadence, Synthesis, CDC, Verifications tools
2w
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ASIC Engineer
New York City, New York, United States
$250k-$300k/yr OnsiteFull Time
4+ YOE4+ years RTL design and verification experience; ASIC design using Synopsys or Cadence flows; experience in front-end, back-end or verification; FPGA/ASIC familiarity; programming experience (Python, C++, Java, Haskell); willingness to learn OCaml.
Hardcaml, OCaml, Synopsys, Cadence, Python, C++, Java, Haskell
3mo
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FPGA Engineer (NJ, Moorestown)
Moorestown, New Jersey, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Familiar with RTL, C/C++, Python, VHDL/Verilog, hardware security, FPGA design, and hardware-software integration; eligible for U.S. government security clearance; willingness to travel ~10%.
VHDL, Verilog, Vivado, GHDL, Questa, Quartus Prime, Zynq, Versal, Stratix, Agilex, AXI, ACE, Avalon, IP core, cocotb, pyuvm, Python, C, C++, Tcl
1mo
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Two Sigma Securities, Hardware Engineer
New York City, New York, United States
$165k-$300k/yr HybridFull Time
1+ YOEMinimum 1 year RTL design and verification experience, proficiency in SystemVerilog and Python, FPGA/ASIC knowledge, timing analysis, network protocol familiarity; C++ is a plus.
SystemVerilog, Python, FPGA, ASIC, C++
1mo
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FPGA Engineer – Intern (US)
New York or Miami
$5k-$6k/wk OnsiteInternship
Pursuing a Bachelor's, Master's or PhD in EE/CE or related field; experience with SystemVerilog or VHDL; knowledge of hardware architecture, RTL, simulation, validation, FPGA synthesis; strong communication and problem-solving skills.
SystemVerilog, VHDL, Python, C, Tcl, Bash
2w
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ASIC Physical Design Engineer
New York City, New York, United States
$250k-$300k/yr OnsiteFull Time
8+ YOE8+ years building and running physical design flows; ability to own PD flow end-to-end, read and write RTL, and use high-level programming to improve hardware tools.
Hardcaml, OCaml, Python, C++, Haskell
1w
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Electronic Hardware Design Engineer
Wayne, Pennsylvania, United States
OnsiteFull Time
5+ YOEBachelor’s or master’s degree in electrical or computer engineering; 5+ years designing, debugging, and bringing up platform or test cards, with digital board design, schematic capture, layout, lab equipment, and system debug experience.
Cadence, ORCAD, Mentor Graphics, Cadence Concept, Allegro, Computer Aided Design (CAD), FPGA, programmable logic devices (PLD), Verilog, C, Python, Visual Basic, Perl, TCL, RTL, DMM, oscilloscopes, logic analyzers
1mo
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Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
3mo
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FPGA Engineer
Hong Kong or London or New York or Singapore or Sydney
$125k-$350k/yr OnsiteFull Time
Bachelor’s/Master’s/PhD in EE, CS, or CE; strong System Verilog/VHDL; hardware/RTL design; low-latency trading knowledge; good communication.
SystemVerilog, VHDL, Python, C, Tcl, Bash
3d
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ASIC Technical Leader - Product Quality & Productization (Hybrid)
San Jose or New York City
$214k-$310k/yr HybridFull Time
20+ YOE20+ years in silicon DFT, test, quality, and program management, including 5+ years in high-reliability hardware; ASIC lifecycle expertise, Synopsys tools, ATE testers, and an electrical or computer engineering degree.
JTAG, SCAN, BIST, RTL, Synopsys, Design Compiler, Tetramax, Spyglass, VCS, ATE, 93K, SPC, JMP, Python, SQL, ISO 9001
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