Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
147 rtl engineer jobs at 40 companies in Pacific Grove, CA
1w
Save
Mark Applied
Hide
RTL integration Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOEBachelor's plus 12+ years experience; deep RTL, UVM/SystemVerilog, synthesis, timing, CDC/RDC, GLS, SDF simulations, NCSim/VCS, Palladium modeling, STA, and strong debugging and communication skills.
RTL, UVM, SystemVerilog, SDF, NCSim, VCS, Palladium
2mo
Save
Mark Applied
Hide
SoC RTL Design Engineer
San Jose or Bangalore
HybridFull Time
8+ YOEBS/MS in Electrical or Computer Engineering; 8+ years in digital IC design with chip infrastructure ownership (clocking, power management, reset/DFT) at block-lead or subsystem level; strong SystemVerilog and infrastructure RTL skills; experience with embedded microcontroller integration and security features.
SystemVerilog, RTL Design, Power Management, Clock Gating, Reset, DFT, BIST, Interrupt Controller, UART, JTAG, PCIe, UCIe
1mo
Save
Mark Applied
Hide
RTL / Circuit IP Design Engineer
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Design and implement RTL/IP features; strong RTL/Verilog/System Verilog, UVM, UPF, SAPR, and simulation/debugging skills; scripting (Python/Perl/Ruby/Makefile/shell); Bachelors or Masters in computer/electrical engineering required.
RTL, UVM, Linux, Windows, Verilog, System Verilog, Python, Perl, Ruby, Makefile, shell, HLS, SAPR, UPF
2mo
Save
Mark Applied
Hide
FE RTL Infrastructure - CAD Engineer
Cupertino, California, United States
OnsiteFull Time
Design and build infrastructure for RTL/CAD to support next-generation high-performance, power-efficient processors and SoCs.
RTL, CAD, SoC
2mo
Save
Mark Applied
Hide
Senior Engineer, RTL Design
San Jose, California, United States
$138k-$206k/yr OnsiteFull Time
5+ YOEBS with 5 years RTL development or MS with 3 years; PhD in Computer/Electrical Engineering; HDL/Verilog; FPGA; PCIe/CXL/NVMe; CAD tools.
Verilog, HDL, CAD tools, Synopsys, Mentor, Cadence, FPGA, PCIe, CXL, NVMe, AXI, DDR4/5, Ethernet
2mo
Save
Mark Applied
Hide
Senior Engineer, GPU RTL Design
Austin or San Jose
$124k-$208k/yr OnsiteFull Time
4+ YOEMaster’s in Electrical/Computer Engineering required for senior/staff; Senior requires 4+ years. Requires RTL design experience (Verilog/SystemVerilog), ASIC front-end flow familiarity, microarchitecture knowledge, and ability to access export-controlled information.
Verilog, SystemVerilog
1mo
Save
Mark Applied
Hide
RTL Design and Architect lead
San Jose or Austin
OnsiteFull Time
10+ YOE10+ years industry experience, Bachelor's/Master's in Electronics/Electrical Engineering, SOC project leadership, RTL design with VHDL/Verilog/SystemVerilog, strong digital design fundamentals, exposure to micro-processor integration and high-speed peripherals, Python familiarity.
VHDL, Verilog, SystemVerilog, Python, GDSII, DDR, PCIe, UCIe, Ethernet
2mo
Save
Mark Applied
Hide
Staff Design Engineer
San Jose, California, United States
$145k-$246k/yr OnsiteFull Time
7+ YOEBachelor's in Computer or Electrical Engineering; 7+ years digital circuit design; RTL and gate-level verification; collaboration across multi-functional teams.
RTL, Verilog, Gate-level verification
1w
Save
Mark Applied
Hide
Senior Design Engineer
San Jose, California, United States
$116k-$198k/yr OnsiteFull Time
5+ YOEBachelor’s degree in computer or electrical engineering and 5+ years of digital circuit design experience. Requires RTL and gate-level verification experience; NAND, leadership, and advanced degrees preferred.
AI tools, Verilog, RTL
1mo
Save
Mark Applied
Hide
Product Development Engineer
San Jose, California, United States
$106k-$154k/yr OnsiteFull Time
5+ YOEBachelor's or Master's in Electrical Engineering (or related) with 5+ years industry experience in IC design/test, DFT/ATPG/MBIST/IJTAG/JTAG, RTL design/synthesis/verification, scripting (Python/Perl/TCL), and semiconductor manufacturing test.
Python, Perl, TCL, ATPG, MBIST, IJTAG, JTAG, RTL, Secure Device Manager (SDM)
1mo
Save
Mark Applied
Hide
Embedded Hardware Engineer
San Jose or Pittsburgh
$160k-$210k/yr OnsiteFull Time
8+ YOE8+ years PCB design and embedded software experience, 5+ years C/C++, experience with silicon bring-up, board bring-up, boot ROM/firmware, RTL/FPGA validation, and embedded platforms (MSP430, STM32, Ambiq Apollo, PIC32).
C, C++, MSP430, STM32, Ambiq Apollo, PIC32, Altium Develop, RTL simulators, FPGA emulators
2mo
Save
Mark Applied
Hide
Senior Engineer, Digital Design Engineering
San Jose, California, United States
$157k-$202k/yr HybridFull Time
2+ YOEMaster's in EE/CE/CS or related, 2+ years digital/mixed-signal design and verification experience, expertise in RTL, Lint, CDC, Verilog/System Verilog, Cadence or Synopsis tools, simulation, synthesis, and ASIC flow.
Cadence, Synopsis, Verilog, System Verilog, RTL, Lint, CDC
3w
Save
Mark Applied
Hide
3D Stacked DRAM-on-Logic Design Engineer
San Jose, California, United States
$150k-$260k/yr OnsiteFull Time
5+ YOEBachelor's in EE,5+ years experience in digital IP/SoC and RTL design for 3D-stacked DRAM,experience with Verilog/VHDL,memory controllers,BIST/DFT/DFD,and strong English communication.
Verilog, VHDL, RTL
2mo
Save
Mark Applied
Hide
Senior Field Security Applications Engineer
Campbell or Austin or United States
$140k-$190k/yr FieldFull Time
5+ YOE5+ years SoC design and verification experience with Verilog/VHDL/SystemVerilog, RTL simulation/emulation tools, strong presentation skills, willingness to travel, US citizenship required.
Verilog, VHDL, SystemVerilog, RTL Simulation, Emulation, Synopsys, Cadence, Siemens, Cycuity Radix, Cycuity HW, FPGA-based Prototyping
2mo
Save
Mark Applied
Hide
Digital Design Engineer - New College Grad
San Jose, California, United States
$99k-$183k/yr HybridFull Time
Master's degree in EE or related field; experience with RTL coding, Verilog models, and analog/digital design; test support and chip bring-up; strong communication and team skills.
Verilog, RTL, Simulations, I2C, SPI, AHB, APB, Bench testing, ATE testing
1mo
Save
Mark Applied
Hide
Design Engineer
San Jose, California, United States
OnsiteFull Time
3+ YOEBS/MS in Electrical/Computer Engineering (or equivalent), 3+ years SystemVerilog RTL design experience, strong digital design fundamentals, power/timing-aware practices, simulation debug, and scripting in Python/Perl/TCL.
SystemVerilog, Python, Perl, TCL, UVM, SVA
3w
Save
Mark Applied
Hide
Physical Design Engineer - Block Level, Subsystem Implementation
San Jose, California, United States
OnsiteFull Time
5+ YOE5+ years physical design experience from RTL synthesis to GDSII sign-off, back-end timing closure on advanced nodes, EDA tool and scripting proficiency, and subsystem PPA optimization.
Cadence (Innovus), Cadence (Genus), Synopsys (Fusion Compiler), PrimeTime, Tempus, Voltus, GDSII, RTL, Unified Power Format (UPF), Tcl, Python, Perl
1w
Save
Mark Applied
Hide
Tech Lead Design Engineer
San Jose, California, United States
$133k-$185k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical or computer engineering, 5+ years of digital design experience, full-chip tapeout experience, and proficiency in Verilog/SystemVerilog, RTL, synthesis, timing closure, CDC, lint, and low-power design.
Verilog, SystemVerilog, PCIe, CXL, Ethernet, NVLink, UALink, COSMOS, UCIe, BIST
1w
Save
Mark Applied
Hide
ASIC Design Engineer
San Jose, California, United States
OnsiteFull Time
BS/MS/PhD in Electrical/Computer Engineering; proficiency in RTL design using Verilog/SystemVerilog, logic and micro-architecture, familiarity with AMBA/PCIe/NAND/DDR, scripting (Python/Perl/TCL), and Linux command-line.
Verilog, SystemVerilog, AMBA, PCIe, NAND, DDR, Python, Perl, TCL, Linux
2mo
Save
Mark Applied
Hide
Applications Engineer
San Jose, California, United States
$130k-$350k/yr OnsiteFull Time
Experience in RTL design/verification, Verilog/SystemVerilog and verification methodologies (UVM); BS/MS in EE/CE/CS; strong customer-facing, presentation, and problem-solving skills.
Synopsys VCS, Cadence Xcelium, Siemens Questa, Verilog, SystemVerilog, UVM, Python, Tcl, Shell
Explore Jobs