128 rtl engineer jobs at 34 companies in Ross, CA
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RTL Engineer
Mountain View, California, United States
$250k-$375k/yr OnsiteFull Time
5+ YOE5+ years RTL/SoC design to silicon, expert Verilog/SystemVerilog, synthesis/timing/CDC/SDC awareness, microarchitecture skills, collaboration across DV/PD/DFT, and scripting in Python/Tcl.
SystemVerilog, Verilog, Python, Tcl, SDC, STA, UPF, HBM, PCIe, SerDes, RISC-V, FPGA
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Senior RTL Engineer, Interconnect Design
San Francisco, California, United States
$225k-$445k/yr HybridFull Time
Senior RTL engineer with deep Verilog/SystemVerilog expertise, SoC interconnect/NoC experience, protocol knowledge (AXI, APB, CXL, PCIe, Ethernet), RTL signoff flows, and track record from microarchitecture through tape-out.
Verilog, SystemVerilog, AXI, APB, CXL, PCIe, Ethernet, RDMA, RoCE, network-on-chip, NoC, FPGA, lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, design-for-test
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
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TPU RTL Design Engineer
Sunnyvale, California, United States
$138k-$198k/yr OnsiteFull Time
2+ YOEBachelor's degree or equivalent,2+ years ASIC RTL design experience focused on clocking/reset/timing-critical RTL,SystemVerilog and scripting (Python/Tcl/Perl) proficiency,experience with clock control and verification.
SystemVerilog, Python, Tcl, Perl
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Sr. RTL Design Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
$170k-$235k/yr OnsiteFull Time
5+ YOEBachelor’s in electrical/computer engineering or computer science; 5+ years of RTL implementation experience.
Verilog, SystemVerilog, Python, EDA tools, HDL simulators, HDL Lint
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Staff SoC RTL Engineer
Burlingame, California, United States
$175k-$230k/yr HybridFull Time
5+ YOERequires BS, MS, or Ph.D. in engineering, 5+ years of SoC/ASIC front-end design, SystemVerilog or Verilog, computer architecture, low-power design, subsystem integration, and VCS with Verilog/C co-simulation.
SystemVerilog, Verilog, VCS, Verilog/C Co-Simulation, FPGA, PCIe, UCIe, DDR, NoC
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Member of Technical Staff, Hardware, RTL Design Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE and 5+ years industry experience with advanced process nodes (7nm or below); strong RTL, synthesis, physical design, and timing tool experience; expertise in computer architecture and silicon delivery.
System Verilog, VCS, Verdi, Fusion Compiler, PrimeTime, C, C++, python, ISA assembly, PCIe, UCIe, HBM, DDR, AXI, CHI, Static Timing Analysis (STA)
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Mixed Signal RTL Design Engineer
Sunnyvale, California, United States
OnsiteFull Time
Specify, design, verify, and assist lab bring-up of advanced mixed-signal circuits (digital side).
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Micro-Architect and RTL Designer
Mountain View, California, United States
$120k-$600k/yr HybridFull Time
4+ YOE4+ years micro-architecture and RTL design experience; SystemVerilog, Python, C/C++; ASIC/SoC concept-to-silicon experience; synthesis and sign-off flows; verification collaboration; US work authorization and export-control compliance.
SystemVerilog, Python, C/C++
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Micro-Architect and RTL Designer
Mountain View, California, United States
$120k-$600k/yr HybridFull Time
4+ YOEConcept-to-silicon ASIC/SoC experience; 4+ years with SystemVerilog, Python, C/C++; production micro-architecture and RTL design experience; synthesis, timing closure, verification collaboration, and high-performance compute or high-speed I/O experience.
SystemVerilog, Python, C/C++
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ASIC Engineer, Design
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's degree or equivalent,6+ years hardware design experience for production silicon,expertise in microarchitecture,RTL and SoC integration,strong communication and collaboration skills.
RTL, Synthesis, Timing Closure, Formal Verification Methodology, SoC, EMR
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AI Silicon, Digital Design Engineer
Palo Alto, California, United States
OnsiteFull Time
8+ YOEB.S. or M.S. in EE/Computer Engineering, 8+ years ASIC/SoC digital design experience, Verilog RTL expertise, EDA tool proficiency, synthesis/timing/LEC experience, and mentorship/communication skills.
Verilog, RTL, EDA tools, Logical Equivalence Checking (LEC), Clock Domain Crossing (CDC), Reset Domain Crossing (RDC)
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Senior FPGA Engineer, LEO Payload FPGA
Sunnyvale, California, United States
$183k-$248k/yr OnsiteFull Time
7+ YOEBachelor's in Electrical Engineering, 7+ years FPGA/System Verilog experience, proficiency with ASIC/FPGA tools, Python test scripting, Xilinx/AMD/Altera FPGAs, RTL/uArchitecture, timing and power optimization, simulation and validation.
System Verilog, Python, Xilinx, AMD, Altera, uArchitecture, RTL, Cocotb, AXI4, AXI Streaming, SerDes, Interlaken, 50G/100G Ethernet
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Staff Silicon Validation Engineer
Palo Alto, California, United States
$186k-$232k/yr OnsiteFull Time
Bachelor's degree in EE/CSE or related, proficiency in C/C++, Python and Linux shell, experience with SoC/FPGA validation preferred (AMD Petalinux, RTL), strong analytical and communication skills.
C, C++, Python, Linux shell, AMD Petalinux, FPGA, RTL
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Principal Subsystem Engineer (Design or DV)
Mountain View or Redmond or Raleigh
$143k-$275k/yr HybridFull Time
8+ YOEBachelor's degree or equivalent experience with 8+ years engineering experience; expertise in digital RTL design or DV, RTL debugging, verification methodology, and cross-team leadership; ability to pass Microsoft cloud background checks.
Verilog, System Verilog, Universal Verification Methodology (UVM), C++, Python, Perl
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Senior DFT Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
8+ YOESenior DFT Engineer with 8+ years in design-for-test for complex digital ASICs/SoCs; expertise with DFT tools; RTL/ASIC test optimization.
Verilog, SystemVerilog, UVM, VHDL, Tcl, Python, Perl, Synopsys DFT Compiler, Tessent, DFTMAX, MBIST, JTAG, ATPG
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Hardware Engineer - FPGA
Milpitas or San Francisco
$152k-$222k/yr OnsiteFull Time
7+ YOEExperienced FPGA/ASIC engineer with RTL (Verilog/SystemVerilog) skills, FPGA tool experience, 7+ years (BS) or 4+ years (MS), verification experience (UVM/VMM) preferred.
Verilog, SystemVerilog, UVM, VMM
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
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ML ASIC Design Engineer
Mountain View or New York City
$175k-$215k/yr HybridFull Time
5+ YOEBS in Computer Engineering or equivalent experience; 5+ years with SystemVerilog, ASIC RTL design, and microarchitecture; 3+ years designing high-performance CPU, GPU, or NPU cores; Python or C++.
SystemVerilog, Python, C++, Chisel, Scala
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