55 rtl engineer jobs at 24 companies in Salem, NH
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Interconnect Micro-architect/RTL Design Engineer
Austin or Boxborough
$156k-$268k/yr HybridFull Time
Experienced RTL design engineer with strong Verilog/System Verilog skills, knowledge of C/C++ and scripting (Perl or Python), digital/high-speed design understanding, and experience with multi-processor coherency, DFT-friendly RTL and post-silicon debug.
Verilog, System Verilog, C, C++, Perl, Python, x86, ARM
2w
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RTL Design Engineer (TERADYNE, North Reading, MA)
North Reading, Massachusetts, United States
$123k-$197k/yr OnsiteFull Time
5+ YOEBSEE or MSEE in electrical engineering or related field and 5+ years of experience. Requires Verilog RTL, logic design, synthesis, timing, CDC, STA, memory, serial, and Python, Tcl, or Make scripting experience.
Verilog, Python, Tcl, Make
1mo
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Principal PCIe Subsystem RTL lead
San Jose or Santa Clara or Austin or Seattle or Boston
HybridFull Time
10+ YOE10+ years digital IC design experience with 4+ years PCIe subsystem design/integration, strong SystemVerilog RTL skills, experience integrating PCIe controller/SerDes PHY, multi-clock-domain design, and ability to lead architectural work.
SystemVerilog, UVM, PCIe, CXL, SerDes
2mo
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FPGA Engineer
Boston, Massachusetts, United States
OnsiteFull Time
RTL proficiency (Verilog or VHDL), real industry FPGA deployment experience, familiarity with major FPGA platforms (Xilinx/AMD, Lattice, Intel/Altera), embedded C/C++ experience, and experience with prototype bring-up and ASIC verification workflows.
Verilog, VHDL, C, C++, RTL, FPGA, Xilinx, AMD, Lattice, Intel/Altera, ASIC, ADC, DAC
3mo
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Senior Engineer, Digital Design Engineering
Wilmington, Massachusetts, United States
$124k-$175k/yr HybridFull Time
2+ YOEMaster’s degree in Electrical/Electronic/Computer Engineering or related field; 2+ years in digital/mixed-signal design and verification; proficiency with RTL, Verilog/SystemVerilog; experience with Cadence or Synopsys tools.
Verilog, SystemVerilog, RTL, Cadence, Synopsys
1mo
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Sr. ASIC Design Engineer, Blink/Ring ASIC Team
North Reading, Massachusetts, United States
$159k-$215k/yr OnsiteFull Time
Bachelor's in Electrical Engineering, knowledge of UVM and Matlab, experience delivering products to volume production, low-power design expertise, RTL coding and debug, and leadership in technical initiatives.
UVM, Matlab, RTL
1mo
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General Support Engineer – Aerospace, Defense & Government (ADG)
Portsmouth, New Hampshire, United States
$96k-$139k/yr OnsiteFull Time
3+ YOEBachelor's in EE/CE,3+ years hardware support or board-level engineering,FPGA and RTL (Verilog/SystemVerilog) experience,lab debug with oscilloscopes/logic/protocol analyzers,Tcl/Python/Java scripting,eligible for U.S. security clearance.
Verilog, SystemVerilog, RTL, DDR, PCIe, Ethernet, Oscilloscope, Logic Analyzer, Protocol Analyzer, Tcl, Python, Java, FPGA
3mo
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FPGA Engineer (MA, Boston)
Boston, Massachusetts, United States
OnsiteFull Time
Experience with RTL, HDL, C/C++, Python; VHDL/Verilog; hardware security; IP core development; FPGA toolchains; Xilinx/Intel devices; simulation and verification; system integration; embedded software testing; cryptography; cocotb/pyuvm.
RTL, VHDL, Verilog, Python, C, C++, Tcl, Vivado, GHDL, Questa, Quartus Prime, Zynq, Versal, Stratix, Agilex, AXI, ACE, Avalon, IP core, Xilinx, FPGA verification tools, cocotb, pyuvm
1mo
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Electrical Engineer
Marlborough, Massachusetts, United States
$75k-$99k/yr OnsiteFull Time
1+ YOEBS/MS in Electrical or Computer Engineering,1-4 years EE experience,schematic design and FPGA RTL with Verilog,OrCAD proficiency,technical writing and strong communication skills.
OrCAD, Verilog, ModelSim, Quartus, Git, SVN, oscilloscope, logic analyzer, frequency generator
3w
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Power Management Design Engineer
Santa Clara or Cambridge or Austin or Boston
$159k-$194k/yr OnsiteFull Time
3+ YOERequires 3+ years in CPU/SoC clocking, reset, and power-management design; RTL proficiency; CPU or SoC development through tapeout; and a BS/MS in a technical discipline or equivalent experience.
Verilog, SystemVerilog, VHDL, SpyGlass, AMBA, AXI, AHB, APB, Scala, Chisel, Bluespec, RISC-V, Git, GitHub, Jira, Confluence, Lint, CDC, RDC, MBIST, DFT, DVFS, RTL
2d
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Electrical Engineer 2
Marlborough, Massachusetts, United States
$69k-$131k/yr OnsiteFull Time
Master’s degree in electrical, computer, or related STEM engineering; RTL coding and simulation in VHDL, Verilog, or SystemVerilog; hardware debugging and root cause investigation experience.
VHDL, Verilog, SystemVerilog, ModelSim, Quartus, Vivado, C, MATLAB, Git, Subversion, Microsoft Office
3mo
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Senior Digital Engineer
Sydney or Sydney or Irvine or Boston or Bangalore or Cambridge or Hangzhou or Taipei or Tokyo or Sydney
OnsiteFull Time
5+ YOE5+ years as Senior Digital Engineer; strong Verilog/SystemVerilog; RTL design; low-power techniques; collaborate with firmware/PHY teams.
Verilog/SystemVerilog, C, Python, Tcl, Shell, Makefiles, UPF/CPF, Scripting and automation
1mo
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Senior FPGA Engineer
Norwood, Massachusetts, United States
OnsiteFull Time
7+ YOE7+ years FPGA/RTL experience, proficiency with RTL design and simulation, Verilog/SystemVerilog, Modelsim/VCS/Xcelium; BS/MS/PhD required; experience with AMD/Altera toolchains preferred.
Modelsim, VCS, Xcelium, Python, C/C++, Verilog, System Verilog
14h
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FPGA Verification Engineer
Waltham, Massachusetts, United States
$166k-$220k/yr OnsiteFull Time
8+ YOEBachelor's in electrical or computer engineering preferred or required, 8+ years developing FPGA HDL firmware, RTL verification experience, Git or Subversion experience, and eligibility for a U.S. Secret clearance.
SystemVerilog, OVM, UVM, VHDL, Verilog, Git, Subversion, Unix, Linux, C, C++, Python, Perl, QuestaSim, Synplify, Quartus, Vivado
1mo
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Senior ASIC Hardware Design Engineer
Westford, Massachusetts, United States
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelor’s or Master’s degree in electrical engineering, computer engineering, computer science, or equivalent experience; 5+ years’ industry experience; Verilog/SystemVerilog, RTL, micro-architecture, VLSI, and Perl/Python scripting expertise.
Verilog, SystemVerilog, Perl, Python
3mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
3w
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Physical Design Engineer
North America or San Francisco or Austin or Boston
HybridFull Time
Hands-on physical design experience for at least one block across multiple advanced-node tapeouts, RTL PPA analysis, microarchitect collaboration, and in-house and outsourced flow management.
1mo
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Principal FPGA Digital Design Engineer - Sign-on Bonus
Nashua, New Hampshire, United States
OnsiteFull Time
6+ YOESecret-clearable engineer with 6+ years FPGA/ASIC experience, VHDL/Verilog RTL coding, timing closure, lab debug, familiarity with high-speed interfaces and revision control.
VHDL, Verilog, Xilinx Vivado, Intel/Altera Quartus, ChipScope, SignalTap, ILA, Modelsim, Questa, GIT, CVS, Clearcase, Subversion, Perl, Tcl, Python, shell, Matlab, Simulink, UVM, SystemVerilog, C, C++
2mo
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Principal FPGA Engineer
Ashburn or Boston or Nashua or Tewksbury
$144k-$192k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CE, 10+ years FPGA hardware development, strong RTL skills (SystemVerilog/Verilog/VHDL), FPGA toolflow experience, lab test/debug proficiency, mentorship/leadership experience, US citizenship required; active security clearance preferred.
ModelSim, Questa, Xilinx ISE, Vivado, Vivado IP Integrator, SystemVerilog, Verilog, VHDL, Zynq MPSoC, Versal Adaptive SoC, UltraScale+, Microchip Libero SoC, Intel Quartus, ChipScope, TCL, oscilloscopes, logic analyzers
3mo
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Modem HW Design Engineer – AI Driven Next Gen Modem Hardware Development
San Diego or Santa Clara or Boxborough
$104k-$192k/yr OnsiteFull Time
1+ YOEBachelor's in engineering or related; 1+ year industry/programming experience; RTL/Verilog/System Verilog and modem development experience; familiarity with synthesis, verification, Unix/Linux shell scripting, Python/Perl.
C, C++, Python, Verilog, System Verilog, Unix/Linux shell scripting, Perl, Makefiles, XML
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