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31 rtl engineer jobs at 13 companies in San Clemente, CA

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Sr. RTL Design Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
$170k-$235k/yr OnsiteFull Time
SpaceX
SpaceX: Designs and launches advanced rockets and satellite internet constellations.
5+ YOEBachelor’s in electrical/computer engineering or computer science; 5+ years of RTL implementation experience.
Verilog, SystemVerilog, Python, EDA tools, HDL simulators, HDL Lint
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Principal FPGA / RTL Design Engineer - Signal Processing
Los Angeles or Irvine
$175k-$225k/yr HybridFull Time
Motorola Solutions
Motorola SolutionsNYSE: MSI: Provides mission-critical communications and public safety technology.
10+ YOEBS in ECE/CS or related; 10+ yrs RTL/FPGA design or 6+ yrs with PhD; Xilinx FPGAs, Vivado; fixed-point DSP; US person.
Xilinx FPGAs, Vivado IDE, Fixed-point arithmetic, Digital Signal Processing, MATLAB, Python, Perl
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FPGA Design Engineer
Los Angeles or Irvine
$100k-$140k/yr HybridFull Time
Silvus Technologies
Silvus TechnologiesNYSE: MSI: Develops advanced mobile ad-hoc network radios for mission-critical communications.
6+ YOESenior FPGA design expert with 6+ years (MS: 4y; PhD: 2y) in fixed-point DSP, multiple clock-domain FPGA designs, Xilinx Vivado.
Xilinx FPGA, Vivado, MATLAB, HDL, FPGA design, RTL coding
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Senior Digital Engineer
Sydney or Sydney or Irvine or Boston or Bangalore or Cambridge or Hangzhou or Taipei or Tokyo or Sydney
OnsiteFull Time
Morse Micro
Morse Micro: Develops low-power Wi-Fi HaLow semiconductor chips for IoT.
5+ YOE5+ years as Senior Digital Engineer; strong Verilog/SystemVerilog; RTL design; low-power techniques; collaborate with firmware/PHY teams.
Verilog/SystemVerilog, C, Python, Tcl, Shell, Makefiles, UPF/CPF, Scripting and automation
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Western Digital
Western DigitalNASDAQ: WDC: Design and manufacture data storage devices and systems.
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
Viasat
ViasatNASDAQ: VSAT: Provider of global satellite-based connectivity and secure communication solutions.
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
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Senior FPGA Engineer
Long Beach, California, United States
$148k-$222k/yr OnsiteFull Time
Relativity Space
Relativity Space: Designing and manufacturing 3D-printed rockets and launch vehicles.
5+ YOEBachelors in EE/Computer Eng or related; 5+ years FPGA development and high-speed digital systems experience in mission-critical applications; RTL/verification/synthesis/timing expertise; cross-functional collaboration skills.
VHDL, Verilog, SystemVerilog, SpinalHDL, Chisel, Vitis, SystemC, Simulink, RISC-V, AMD Xilinx, Intel, Microchip, CI/CD
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Senior Principal Engineer Digital ASIC Design/Manager
San Diego, California, United States
$214k-$348k/yr OnsiteFull Time
Kyocera
KyoceraTokyo Stock Exchange: 6971: Manufactures advanced ceramic components and high-tech electronic equipment.
15+ YOEBS or MS in Electrical Engineering; 15 years in Digital ASIC design; leadership; cross-functional collaboration; RTL/verification; experience with mixed-signal interfaces is a plus.
Verilog, SystemVerilog, LINT, LEC, RDC/CDC, SDF, Genus, Conformal, Innovus, Spyglass Lint, TetraMax, Xcelium, Cadence, Synopsys PrimeTime, VCS, UGV, UVM
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Digital Design Engineer
Irvine, California, United States
$98k-$144k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
1+ YOE1+ years experience designing and verifying high-performance communications/DSP ASICs; strong RTL (Verilog/System Verilog) and UNIX-based EDA tool skills; experience with verification, synthesis, lint, CDC, power analysis; MATLAB/C++ a plus.
Verilog, System Verilog, UNIX, EDA, MATLAB, C/C++
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Staff FPGA Design Engineer
Irvine, California, United States
$150k-$190k/yr OnsiteFull Time
Terran Orbital
Terran OrbitalNYSE: LMT: Manufactures modular spacecraft for aerospace and defense missions.
8+ YOEBachelor's in EE/CE, 8+ years FPGA RTL architecture/development/verification, strong SystemVerilog or VHDL skills, experience with Microship Polarfire/AMD Zynq/Versal/Ultrascale, verification methodologies, Git, Python/Tcl/Bash, C/C++ on Linux, and eligibility for DoD security clearance.
SystemVerilog, VHDL, Microship Polarfire, AMD Zynq US+, Versal, AMD Ultrascale, Vivado, Mentor Modelsim/Questasim, AXI, PCIe, DDR4, DDR5, JESD204B, JESD204C, 100Gb ethernet, SPI, I2C, UART, CAN FD, LVDS, Git, Python, Tcl, Bash, Linux, C/C++
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Senior ASIC/FPGA Verification Engineer (Onsite)
El Segundo or Fullerton
$96k-$182k/yr OnsiteFull Time
RTX
RTXNYSE: RTX: RTX provides advanced aerospace and defense systems and services.
5+ YOEActive transferable U.S. SECRET clearance and U.S. citizenship, STEM degree (BS or advanced) with 5+ years (BS) or 3+ years (advanced) experience, RTL verification using VHDL/Verilog/SystemVerilog, testbench and coverage, and revision control (Git/Subversion).
SystemVerilog, OVM, UVM, VHDL, Verilog, Git, Subversion, QuestaSim, Synplify, Quartus, Vivado, Unix, Linux
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Principal Design Validation & Test (DVT) Engineer
Irvine, California, United States
OnsiteFull Time
Celero Communications
Celero Communications: Developing high-performance coherent DSP technology for AI connectivity.
8+ YOE8+ years post-silicon validation/DVT experience with complex ASICs/SoCs; Bachelor's in EE/CE/CS or related; Python skills; lab equipment and high-speed protocol expertise; strong debug and communication skills.
JTAG, Python, oscilloscopes, BERTs, protocol analyzers, network analyzers, logic analyzers, Ethernet traffic generators, power measurement equipment, PCIe, Ethernet, SerDes, CXL, SPI, I²C, MDIO, RTL
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Field Application Engineer – PowerPro
Austin or Costa Mesa or San Diego or Santa Clara
$147k-$293k/yr HybridFull Time
Siemens
SiemensXETRA: SIE: Manufactures industrial automation, infrastructure, and energy technology systems.
3+ YOE3+ years RTL design experience with Verilog/SystemVerilog/VHDL, RTL power analysis knowledge, scripting with Tcl/Python, BS/MS in EE/CS or related, strong communication and customer-facing skills.
PowerPro, Verilog, SystemVerilog, VHDL, Tcl, Python, PrimePower, PowerArtist, UPF, CPF
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