3mo
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RTL Design Engineer
San Diego, California, United States
OnsiteFull Time
Bachelor's in Electrical Engineering; strong RTL design, Verilog/SystemVerilog, DSP concepts, and lab bring-up experience; verification and scripting familiarity.
Verilog, SystemVerilog, Python, Perl, Linter, Clock-domain crossing checkers, Synthesis, Static timing analysis, DFT, Assertions
2mo
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Processor ASIC RTL Design Engineer
San Diego, California, United States
$127k-$191k/yr OnsiteFull Time
2+ YOE2+ years RTL and microprocessor design experience; strong RTL design in System Verilog/Verilog, familiarity with linting, CDC, LEC, CLP, synthesis, static timing analysis, PLDRC, and low-power techniques; BS/MS/PhD in EE/CS/CE or related.
System Verilog, Verilog, RTL, GDS2, linting, CDC, LEC, CLP, synthesis, static timing analysis, PLDRC
1mo
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Sr. RTL Design Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
$170k-$235k/yr OnsiteFull Time
5+ YOEBachelor’s in electrical/computer engineering or computer science; 5+ years of RTL implementation experience.
Verilog, SystemVerilog, Python, EDA tools, HDL simulators, HDL Lint
1mo
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Principal FPGA / RTL Design Engineer - Signal Processing
Los Angeles or Irvine
$175k-$225k/yr HybridFull Time
10+ YOEBS in ECE/CS or related; 10+ yrs RTL/FPGA design or 6+ yrs with PhD; Xilinx FPGAs, Vivado; fixed-point DSP; US person.
Xilinx FPGAs, Vivado IDE, Fixed-point arithmetic, Digital Signal Processing, MATLAB, Python, Perl
3w
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Staff/Sr. Staff GPU Engineer – Shader System RTL Design/Microarchitecture
San Diego, California, United States
$150k-$244k/yr OnsiteFull Time
8+ YOEBS/MS/PhD or equivalent,8+ years (Staff) /10+ years (Sr Staff) in RTL/microarchitecture for GPU or high-performance SoC; strong SystemVerilog/Verilog/VHDL,C/C++,Python skills; RTL debug, PPA optimization, and cross-team collaboration.
SystemVerilog, Verilog, VHDL, C, C++, Python, Perl, Tcl, Shell, Vulkan, Direct3D, OpenGL, OpenGL ES, Metal, OpenCL
1mo
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FPGA Design Engineer
Los Angeles or Irvine
$100k-$140k/yr HybridFull Time
6+ YOESenior FPGA design expert with 6+ years (MS: 4y; PhD: 2y) in fixed-point DSP, multiple clock-domain FPGA designs, Xilinx Vivado.
Xilinx FPGA, Vivado, MATLAB, HDL, FPGA design, RTL coding
1mo
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ASIC Design Engineer I, Satellite Communications
San Diego, California, United States
$123k-$170k/yr OnsiteFull Time
2+ YOEBachelor's in Electrical Engineering; 2+ years in digital logic/DSP design; RTL implementation; DSP algorithms optimization.
MATLAB, RTL, UVM, SystemC, DPI-C, Verilog, VHDL
2mo
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Programmable Logic Design Engineer
Germantown or Carlsbad or Independence or Englewood
$156k-$246k/yr OnsiteContract
5+ YOEBachelor's degree in Electrical/Computer Engineering; 5-8 years FPGA design; SystemVerilog; RTL design for signal processing; FPGA modules; strong communication; distribution teamwork.
System Verilog, Verilog, VHDL, Xilinx Vivado, RTL design, FPGA design, Testbench development, Simulation
2mo
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Distinguished Engineer - Digital Design
San Diego, California, United States
$212k-$314k/yr OnsiteFull Time
17+ YOESenior-level expertise in SystemVerilog, RTL design, PCIe/CXL, and complex SoC architectures; 17+ years (or 12-15 with MS, or 10-12 with PhD); strong leadership and communication.
SystemVerilog, RTL, SVA, Synthesis, Formal verification, Debug tooling, Python, Perl, Tcl, Unix shell
2mo
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Senior Digital Engineer
Sydney or Sydney or Irvine or Boston or Bangalore or Cambridge or Hangzhou or Taipei or Tokyo or Sydney
OnsiteFull Time
5+ YOE5+ years as Senior Digital Engineer; strong Verilog/SystemVerilog; RTL design; low-power techniques; collaborate with firmware/PHY teams.
Verilog/SystemVerilog, C, Python, Tcl, Shell, Makefiles, UPF/CPF, Scripting and automation
3mo
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Digital Design Engineer
San Diego, California, United States
$190k-$220k/yr OnsiteFull Time
8+ YOELead digital design and verification, RTL synthesis, low-power audio processing, 8+ years in digital blocks for high-performance mixed-signal ICs; strong EDA (Cadence) knowledge.
Cadence, Conformal, Genus, Tempus
3mo
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Senior ASIC DV Engineer
San Jose or Irvine
$141k-$226k/yr OnsiteFull Time
12+ YOEBachelor’s in Engineering with 12+ years, or Master’s with 10+ years, or PhD with 7+ years; MS/PhD preferred.
UVM, AMS, Spice, RTL, Gate-level verification, ATE
2mo
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Staff Digital Design Engineer
San Diego, California, United States
$139k-$232k/yr OnsiteFull Time
6+ YOEDesign digital subsystems for phased array and communication systems; RTL/SystemVerilog; SoC integration; embedded software in C; timing analysis; ECOs; SPI/QSPI and high-speed serial interfaces; Bachelor's or Master's in Electrical Engineering; 6+ years digital ASIC/SoC design.
SystemVerilog, Verilog, C, SPI, QSPI, JESD204B/C, Synthesis, Place-and-Route, UVM, ECOs, RISC-V, embedded software
3w
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Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
2+ YOEUS citizenship with ability to obtain U.S. Secret clearance, Bachelor\u0000s degree in a relevant field, experience with ASIC/FPGA design or verification, and RTL experience with Verilog/VHDL/SystemVerilog.
Verilog, VHDL, SystemVerilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, ARM, JESD204C, PCIe, Ethernet
1mo
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Staff FPGA Design Engineer
Irvine, California, United States
$150k-$190k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CE, 8+ years FPGA RTL architecture/development/verification, strong SystemVerilog or VHDL skills, experience with Microship Polarfire/AMD Zynq/Versal/Ultrascale, verification methodologies, Git, Python/Tcl/Bash, C/C++ on Linux, and eligibility for DoD security clearance.
SystemVerilog, VHDL, Microship Polarfire, AMD Zynq US+, Versal, AMD Ultrascale, Vivado, Mentor Modelsim/Questasim, AXI, PCIe, DDR4, DDR5, JESD204B, JESD204C, 100Gb ethernet, SPI, I2C, UART, CAN FD, LVDS, Git, Python, Tcl, Bash, Linux, C/C++
2mo
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Principal DFT Engineer
Carlsbad, California, United States
$155k-$193k/yr OnsiteFull Time
9+ YOELead DFT on SOC; design/verify DFT; optimize test yield and cost; mentor team.
Verilog, VHDL, RTL, ATPG, MBIST, JTAG, DC/AC analysis, Synthesis, Simulation, ATE
2w
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Sr. Staff/Staff Engineer, Digital Design
San Diego or San Jose
OnsiteFull Time
Deep RTL/SystemVerilog expertise, SoC architecture knowledge, familiarity with AXI/AHB/APB/OBI, multi-clock/multi-power-domain and timing closure experience, skills with SystemVerilog, Python, Tcl, UPF, and security technologies (Arm TrustZone, Secure Boot, PSA Level 2+); MS/PhD preferred.
SystemVerilog, Python, Tcl, UPF, AXI, AHB, APB, OBI, Arm TrustZone
3mo
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Principal Engineer Digital Design
Irvine or California or Dallas or Texas
$164k-$241k/yr HybridFull Time
12+ YOEBachelor's degree in EE/Computer Engineering, 12+ years RTL design experience (Verilog/System Verilog), DSP algorithm implementation, fixed-point math, MATLAB/C/C++, FPGA/ASIC experience, and familiarity with EDA tools (Synopsys Design Compiler, Cadence).
Verilog, System Verilog, HDL, MATLAB, Simulink, C, C++, Synopsys Design Compiler, Cadence
1mo
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Field Application Engineer – PowerPro - Job Detail | Careers Marketplace - Siemens
Austin or Costa Mesa or Santa Clara or San Diego
$147k-$293k/yr HybridFull Time
Strong RTL design experience (Verilog/SystemVerilog/VHDL), knowledge of digital design and synthesis/verification flows, RTL power analysis experience, scripting (Tcl, Python), BS/MS in EE/CS or related field, strong communication and problem-solving skills.
PowerPro, Verilog, SystemVerilog, VHDL, Tcl, Python, PrimePower, PowerArtist, UPF, CPF, Microsoft Copilot, OpenAI APIs
1mo
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Senior React.Js Developer - Ecommerce Domain
Chennai or Bengaluru or Porto or Aveiro or Coimbra or Leicester or San Diego
HybridFull Time
Senior React.js developer with expertise in React.js, TypeScript, JavaScript, frontend architectures, state management (Redux/Context API/Zustand), Next.js preferred, testing (Jest, RTL, Cypress/Playwright), Git, CI/CD, and mandatory e-commerce domain experience.
React.js, TypeScript, JavaScript (ES6+), HTML5, CSS3, SCSS, Redux, Redux Toolkit, Context API, Zustand, Next.js, Jest, React Testing Library, Cypress, Playwright, Git, GitHub, GitLab, Bitbucket, RESTful APIs, GraphQL, CI/CD, Tailwind CSS, AWS, Azure, GCP
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