13 rtl engineer jobs at 8 companies in Sanborn, NY
3mo
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RTL Design Engineer, Sr Staff
Toronto, Ontario, Canada
OnsiteFull Time
4+ YOEBachelor's+6 / Master's+5 / PhD+4 years in ASIC/SoC RTL design; strong Verilog/VHDL RTL experience, synthesis, LEC/formal, timing closure, UPF, lint/CDC, verification collaboration, post-silicon debug, and strong communication skills.
Verilog, VHDL, UPF, CLP, Lint, CDC, LEC, Design Compiler, FPGA
2w
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Senior Design Engineer - Security IP
Toronto, Ontario, Canada
$126k-$170k/yr HybridFull Time
Bachelor's or graduate degree in computer science or electrical/computer engineering preferred; advanced Verilog RTL, SoC security, architecture, verification, EDA, synthesis, timing, constraints, and scripting experience required.
Verilog, RTL, EDA, AXI, AHB, CDC, RDC, X-Propagation, LINT, UPF, Perl, Python, TCL, ARM, SystemVerilog, UVM, OVM, Portable Stimulus
3w
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Staff PCIe Design Engineer
Toronto, Ontario, Canada
$159k-$216k/yr HybridFull Time
10+ YOEBachelors or Master’s in CS/Electrical/Computer Engineering,10+ years SoC/subsystem design experience, Verilog RTL development, PCIe/CXL/UCIe integration, static design checks, scripting (Perl/Python).
Verilog HDL, RTL, PCIe, CXL, UCIe, Ethernet, Perl, Python, CDC, RDC, X-Propagation, Linting
2w
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DSP Systems Engineer, Staff
Toronto, Ontario, Canada
$111k-$161k/yr OnsiteFull Time
2+ YOERequires a bachelor's degree and 4+ years, master's and 3+ years, or PhD and 2+ years in systems engineering or related work. Requires MATLAB, Python, C/C++, DSP architecture, SerDes, RTL, and digital design expertise.
MATLAB, Python, C, C++, RTL, Firmware, ADC
1mo
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DFT Engineer, Senior
Toronto, Ontario, Canada
$90k-$134k/yr OnsiteFull Time
2+ YOEBachelor's in CS/Electrical/Engineering plus 2+ years hardware experience (or Master's 1+ year or PhD). Skills in DFT, ATPG, MBIST/LBIST, RTL verification, and scripting required.
Python, Tcl, Perl
3mo
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Lead Digital Verification Engineer
Montreal or Ottawa or Toronto
$90k-$166k/yr OnsiteFull Time
Bachelor's in Electrical/Computer Engineering or Computer Science; knowledge of verification architectures, UVM, SVAs; digital RTL verification; test plan and coverage development; strong communication; willingness to travel
SystemVerilog, UVM, Verifications, Python, Perl, Ruby, Sed, Awk, SystemVerilog Assertions, PCIe, USB, SATA, Ethernet, DisplayPort, HDMI, Cadence tools, Formal verification, Mixed-signal verification, CPF, UPF
1mo
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DFT Engineer (Senior to Staff level)
Toronto, Ontario, Canada
$90k-$134k/yr OnsiteFull Time
10+ YOE10+ years SoC RTL/DFT experience preferred; strong knowledge of DFT EDA tools, Verilog/VHDL/SystemVerilog, JTAG/iJTAG/BIST standards, scan insertion and ATPG, and scripting (TCL/Python/Perl).
Siemens, SNPS, Cadence, Verilog, VHDL, SystemVerilog, TCL, Python, Perl, FPGA, ATPG, SDF, JTAG (1149.1/1149.6/1500), iJTAG (1687)
2mo
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Static Timing Analysis (STA) Engineer
Toronto, Ontario, Canada
$103k-$149k/yr OnsiteFull Time
6+ YOE6+ years STA experience for ASIC or FPGA, strong STA fundamentals, experience with PrimeTime or equivalent, RTL (Verilog/SystemVerilog), synthesis/place & route, and scripting (Tcl/Python) preferred. Bachelor's degree in EE/CE or related field.
PrimeTime, Tcl, Python, Verilog, SystemVerilog
3mo
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Physical Design Manager
Toronto, Ontario, Canada
$180k-$220k/yr OnsiteFull Time
12+ YOE2+ MgmtLead a PD team, own RTL-to-GDSII, floorplanning, P&R, timing closure; mentor engineers.
Cadence Innovus, Synopsys Fusion Compiler, ICC2, Synthesis tools, Verilog, SystemVerilog, Tcl, Python, Perl
2d
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Sr. Manager, Physical Design Engineering, Annapurna Labs
Toronto, Ontario, Canada
$180k-$300k/yr OnsiteFull Time
10+ YOE5+ MgmtRequires 10+ years ASIC/SoC physical design, 5+ years managing teams of 8+ engineers, multiple advanced-node tapeouts, RTL-to-GDSII expertise, EDA proficiency, and expert TCL, Python, and Perl scripting.
Synopsys, Fusion Compiler, ICC2, PrimeTime, StarRC, RedHawk-SC, Cadence, Innovus, Tempus, Quantus, Voltus, Siemens Calibre, TCL, Python, Perl, RTL2GDS, AI/ML, PDK, UPF, UCIe, CoWoS, EMIB, InFO, SoIC, Foveros, CXL, TSMC, Samsung, Intel Foundry Services, IEEE
2mo
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Technology VDC Coordinator, Technology Construction
Toronto, Ontario, Canada
HybridFull Time
CAD/BIM proficiency with Revit/Navisworks; coordinate drawings with multi-disciplinary teams; knowledge of AV, DAS, RTLS; proficient with MS Office and BIM tools.
Revit, Navisworks, AutoCAD, ACC Platform, Revizto, Bluebeam, Power BI, Microsoft Excel, Microsoft Word, PowerPoint
2mo
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Member of Technical Staff - Low Level & Kernels Capabilities
San Francisco or Toronto or Seattle
$200k-$350k/yr OnsiteFull Time
Experienced low-level systems engineer fluent in C/C++/CUDA and Python, kernel and kernel-optimization experience, hardware-aware coding, familiarity with LLMs, and ability to design robust, ungameable RL environments.
C, C++, CUDA, Python, assembly, cuBLAS, FFTW, OpenSSL, FPGA, RISC-V, SIMD, AVX, TPU, RTL, HDL, HLS, MLIR, LLVM, Mojo, Triton, gem5, Lean, Coq, SMT
1mo
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SoC Interconnect Technology Team Lead
Toronto, Ontario, Canada
$286k-$336k/yr HybridFull Time
15+ YOE15+ years in SoC architecture/design with interconnect expertise, experience delivering large-scale SoCs, deep protocol knowledge (coherent and non-coherent), performance modeling, and leadership of cross-functional teams.
AMBA ACE, CHI, CCIX, CXL, AXI, NoC, RTL