18 rtl engineer jobs at 12 companies in New York
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
1w
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Hardware Engineer, RTL/PD
New York City or London or Zurich or Palo Alto or Copenhagen or Seoul
$200k-$285k/yr OnsiteFull Time
Production SystemVerilog RTL experience, synthesis and place-and-route through tapeout, experience with backend flows and timing closure, familiarity with formal methods and post-silicon bring-up; multiple tapeouts preferred.
SystemVerilog, RISC-V, GDSII, CTS, DFT, LVS, DRC
2mo
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Senior FPGA Engineer
Chicago or New York City or London
$225k-$325k/yr OnsiteFull Time
3+ YOEBachelor's in Computer or Electrical Engineering, 3+ years FPGA/hardware engineering experience, RTL/Verilog expertise, FPGA design flow experience, knowledge of TCP/IP, strong autonomous and problem-solving skills.
Verilog, System Verilog, RTL, XILINX, ALTERA, TCP/IP, synthesis, place & route, static timing analysis
2mo
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Senior FPGA Engineer
Chicago or New York City or London or United States or Canada or Europe or Asia
OnsiteFull Time
3+ YOEBachelor's in Computer/Electrical Engineering, 3+ years FPGA/hardware experience, Verilog/System Verilog and RTL skills, FPGA design flow (synthesis, place & route, static timing), SoC and TCP/IP knowledge, lab debugging, EM/board characterization.
Verilog, System Verilog, RTL, TCP/IP, XILINX, ALTERA
2mo
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Staff Engineer, Digital ASIC Design (CONTRACT)
Burlington or New York
HybridContract
8+ YOEBS/MS/PhD in EE/CE; 8+ yrs in digital IC/ASIC/SoC; RTL ownership; SystemVerilog/Verilog; high-throughput datapaths; silicon constraints; SV/UVM; Python/cocotb; post-silicon bring-up.
SystemVerilog/Verilog, UVM, Python, cocotb, RTL, RTL verification, Fixed-point modeling
1mo
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DSP Engineer
New York or New Jersey or United States
RemoteFull Time, Contract
7+ YOEMS in Electrical Engineering (DSP focus) required; 7+ years FPGA design with synthesizable RTL, VHDL/Verilog/SystemVerilog, Vivado/Vitis toolchains, high-speed serial interfaces (JESD204B/C, PCIe, Ethernet), SOC/FPGA platforms, and strong lab debugging skills.
Vivado, Vitis, VHDL, Verilog, SystemVerilog, JESD204B, JESD204C, PCIe Gen3, PCIe Gen4, Ethernet, Aurora, AMD RFSoC, Zynq Ultrascale+, Versal AI Core, Microchip PolarFire, AXI
3d
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ML ASIC Design Engineer
Mountain View or New York City
$175k-$215k/yr HybridFull Time
5+ YOEBS in Computer Engineering or equivalent experience; 5+ years with SystemVerilog, ASIC RTL design, and microarchitecture; 3+ years designing high-performance CPU, GPU, or NPU cores; Python or C++.
SystemVerilog, Python, C++, Chisel, Scala
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FPGA Engineer
New York or New Jersey or United States
RemoteFull Time
5+ YOE5–7 years FPGA/ASIC experience, DSP proficiency, RTL (VHDL/Verilog/SystemVerilog), FPGA toolchains, high-speed interfaces, MATLAB/Simulink or Python, and SoC/embedded integration experience.
VHDL, Verilog, SystemVerilog, Xilinx Vivado, Vitis, Intel Quartus, JESD204, LVDS, SERDES, MATLAB, Simulink, Python, RFSoC, Xilinx/AMD Versal, Zynq, Git, eCPRI, Ethernet
1w
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ASIC Engineer
New York City, New York, United States
$250k-$300k/yr OnsiteFull Time
4+ YOE4+ years RTL design and verification experience; ASIC design using Synopsys or Cadence flows; experience in front-end, back-end or verification; FPGA/ASIC familiarity; programming experience (Python, C++, Java, Haskell); willingness to learn OCaml.
Hardcaml, OCaml, Synopsys, Cadence, Python, C++, Java, Haskell
3w
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Two Sigma Securities, Hardware Engineer
New York City, New York, United States
$165k-$300k/yr HybridFull Time
1+ YOEMinimum 1 year RTL design and verification experience, proficiency in SystemVerilog and Python, FPGA/ASIC knowledge, timing analysis, network protocol familiarity; C++ is a plus.
SystemVerilog, Python, FPGA, ASIC, C++
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FPGA Engineer – Intern (US)
New York or Miami
$5k-$6k/wk OnsiteInternship
Pursuing a Bachelor's, Master's or PhD in EE/CE or related field; experience with SystemVerilog or VHDL; knowledge of hardware architecture, RTL, simulation, validation, FPGA synthesis; strong communication and problem-solving skills.
SystemVerilog, VHDL, Python, C, Tcl, Bash
1mo
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FPGA Design Engineer
New York City, New York, United States
$200k-$280k/yr OnsiteFull Time
Proven FPGA experience bringing RTL to timing-closed hardware; expert SystemVerilog/VHDL and Xilinx Vivado; PCIe and common bus protocols; strong Python/C++ for automation; board bring-up and lab debugging skills.
SystemVerilog, VHDL, Xilinx Vivado, ILA, Vivado Analyzer, Python, C++, PCIe, AXI, AHB, SPI, UART, JTAG, HAPS, VCU118, VPK180, Cocotb, UVM, OSVVM, hls4ml, FINN, GitLab CI, Docker, oscilloscope, logic analyzer
1w
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ASIC Physical Design Engineer
New York City, New York, United States
$250k-$300k/yr OnsiteFull Time
8+ YOE8+ years building and running physical design flows; ability to own PD flow end-to-end, read and write RTL, and use high-level programming to improve hardware tools.
Hardcaml, OCaml, Python, C++, Haskell
4w
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Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
2w
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Senior Digital ASIC Design Engineer
Upton, New York, United States
$115k-$145k/yr OnsiteFull Time
7+ YOEBachelor's in EE/CE/applied physics, 7+ years digital ASIC design, SystemVerilog/Verilog RTL, CAD/EDA tool experience, strong timing/CDC/low-power knowledge, and collaboration with mixed-signal, verification, and firmware teams.
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, AXI, AHB, APB, Wishbone, I2C, SPI, JTAG, Tcl, Python, Perl, Make, shell
3mo
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FPGA Engineer
Hong Kong or London or New York or Singapore or Sydney
$125k-$350k/yr OnsiteFull Time
Bachelor’s/Master’s/PhD in EE, CS, or CE; strong System Verilog/VHDL; hardware/RTL design; low-latency trading knowledge; good communication.
SystemVerilog, VHDL, Python, C, Tcl, Bash
1mo
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Senior CPU Performance Architect
Austin or Portland or Mountain View or Poughkeepsie
$163k-$237k/yr OnsiteFull Time
8+ YOE8+ years in microprocessor architecture and performance, Bachelor's in EE/CE/CS or equivalent, RN? (ignore) BLS? (ignore) Experience with performance modeling, EM/RTL correlation, and system software knowledge.
ARM, RISC-V, x86, RTL, Linux
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Senior Engineering Manager API Platform
Minnesota or Arizona or New York or Illinois
$118k-$261k/yr RemoteFull Time
7+ YOE7+ Mgmt7+ years leadership managing ICs, 7+ years building enterprise applications, 5+ years JavaScript, 3+ years TypeScript and Node.js, experience with API gateways (Kong, Apigee, APIM), distributed workflows (Temporal), and strong security/authentication knowledge.
GraphQL, OAuth, OIDC, JWTs, Apigee, APIM, Kong, Temporal, JavaScript, TypeScript, Node.js, Git, Jest, RTL, Cypress, Playwright, Kubernetes, Docker, GHA, CI/CD
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