28 rtl engineer jobs at 6 companies in Sumas, WA
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Senior RTL Design Engineer
Markham or Vancouver or Ottawa
HybridFull Time
Hands-on IP RTL design experience, Verilog HDL coding, AI-assisted RTL integration, timing/LINT/CDC closure, multi-clock-domain design; Bachelors in Computer or Electrical Engineering.
Verilog HDL, AI-generated RTL, lint, CDC, PCI Express (PCIe)
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RTL Design Engineer
Markham or Vancouver
$155k-$233k/yr HybridFull Time
Senior RTL design experience owning digital IP/subsystems from architecture to tape-out; Verilog/SystemVerilog, VCS, Perl/Shell, RTL quality flows (Lint, CDC/RDC, synthesis, LEC, STA); Bachelor's or Master's in EE/CompE.
Verilog, SystemVerilog, VCS, Perl, Shell, Lint, CDC/RDC, synthesis, LEC, STA
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Senior RTL Design Engineer
Markham or Vancouver or Ottawa
$155k-$233k/yr HybridFull Time
Hands-on RTL design and verification experience using Verilog HDL, AI-assisted RTL methodologies, multi-clock-domain design, lint/CDC closure, and high-speed I/O protocols; BSc in Computer or Electrical Engineering.
Verilog HDL
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Principal RTL Design Engineer
Burnaby, British Columbia, Canada
$86k-$186k/yr OnsiteFull Time
2+ YOE2+ years ASIC development experience; strong RTL design/verification skills in Verilog/SystemVerilog/VHDL; experience with lab debugging, C/C++, scripting (Python, Perl, TCL, Shell); degree in electrical/computer engineering or related field.
Verilog, SystemVerilog, VHDL, C, C++, Python, Perl, TCL, Shell, oscilloscope, logic analyzer
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Camera Frontend Implementation Engineer
Vancouver, British Columbia, Canada
$90k-$135k/yr OnsiteFull Time
2+ YOEDegree in engineering or science (BS/MS/PhD) with 1–2+ years ASIC design experience; experience with RTL-to-GDS2 flow, synthesis, static timing analysis, formal/low-power verification, physical design, ECO generation, and scripting.
RTL, GDS2, Netlist, synthesis, static timing analysis, formal verification, physical design, ECO generation
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SoC Development Engineer
Vancouver, British Columbia, Canada
$91k-$135k/yr HybridFull Time
Bachelor’s in EE/CE/CS with strong debugging, digital logic design, RTL/verification (UVM/FPV); proficient in C/C++, Python, Verilog/SystemVerilog; internship/1+ year experience preferred.
C, C++, Python, Java, Verilog, SystemVerilog, UVM, FPV, Jira, Confluence, NVMe, PCIe, DDR, ARM
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Full Stack Web Developer (Next.js / TypeScript / Node.js)
Vancouver, British Columbia, Canada
$105k-$143k/yr HybridFull Time
3+ YOE3+ years experience with Next.js, TypeScript, and Node.js; experience with NestJS, React, Contentful, third-party API integrations, Git, testing (Jest/RTL), CI/CD, REST/GraphQL; Bachelor's degree in CS/Engineering or equivalent.
Node.js, NestJS, Contentful, React, Next.js, JavaScript, TypeScript, Git, Jest, React Testing Library, GitLab, GitHub Actions, RESTful, GraphQL, CDN
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ASIC Physical Design Technical Leader
Vancouver, British Columbia, Canada
$142k-$182k/yr HybridFull Time
8+ YOEBachelor's/Master's/PhD in Electrical Engineering with extensive physical design experience; Fullchip and RTL-to-GDSII flow experience in advanced process nodes; proficiency with EDA tools, UPF, Python and AI tools.
Innovus, Tempus, Primetime, Redhawk, Voltus, Calibre, Pegasus, Python, UPF, AI tools
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