11 rtl engineer jobs at 7 companies in Towson, MD
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Digital Design Engineer - Level 5 - Linthicum
Linthicum, Maryland, United States
$186k-$279k/yr OnsiteFull Time
7+ YOEDegree in EE/CE/CS (Bachelor’s+12yr or Master’s+10yr or PhD+7yr), FPGA/ASIC/HDL (Verilog, VHDL) experience, FPGA IDEs (Xilinx, Microsemi), test/verification and RTL debug, mentoring skills, U.S. citizenship and ability to obtain Top Secret clearance.
Xilinx, Microsemi, HDL, Verilog, VHDL, RTL
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
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Firmware Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in CE/EE/CS, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado/SoC FPGAs, TCP/UDP/IP and serial protocols, Bash/Python scripting; U.S. Person required.
Verilog, SystemVerilog, Vivado Design Suite, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, Bash, Python, git, Bitbucket CI, Jenkins
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Senior ASIC Digital Design Engineer
Annapolis Junction or Boise or Salt Lake City or Bloomington or United States
$142k-$150k/yr RemoteFull Time
5+ YOEBachelor's in Electrical/Computer Engineering (or related) with 5+ years experience (Master's+3 acceptable), U.S. citizenship, ability to obtain DoD Secret clearance, 5–8+ years ASIC/FPGA RTL design experience, formal verification and verification-process experience, JIRA and Microsoft Office proficiency.
JIRA, Microsoft Office, STA
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Embedded FPGA Engineer
McLean, Virginia, United States
$87k-$198k/yr OnsiteFull Time
3+ YOE3+ years developing FPGA/SDR solutions; proficiency with Verilog/VHDL/SystemVerilog/HLS, Vitis/Vivado/Xilinx toolchains, Python/C++, MATLAB, Linux, Agile tools (Jira, Confluence); ability to obtain TS/SCI clearance; bachelor’s in EE or CE required.
Python, C++, MATLAB, Jira, Confluence, Verilog, VHDL, SystemVerilog, HLS, Vitis HLS, Vitis, Vivado, Tcl, Linux, UNIX, AXI-Stream, AXI-Lite, DMA, RTL, SDR, SOSA, VPX, GPU, Logic Analyzer, Oscilloscope, Spectrum Analyzer
2w
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FPGA Verification Engineer Level 3/4 - Linthicum
Linthicum, Maryland, United States
$120k-$179k/yr OnsiteFull Time
3+ YOEU.S. citizen required. FPGA verification experience with VUnit, HDL (SystemVerilog/Verilog/VHDL), testbench and coverage-driven verification, RTL debug, test plan development; ability to obtain DoD Secret/Top-Secret clearance.
VUnit, SystemVerilog, Verilog, VHDL, Synopsys, Mentor Graphics, SystemVerilog Assertions (SVA), Bash, Perl, Python, Tcl, Makefile, Xilinx, MicroChip, Kintex, Zynq ultrascale+, RTG4
2w
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FPGA Verification Engineer Level 3/4 - Linthicum
Linthicum Heights, Maryland, United States
$120k-$179k/yr OnsiteFull Time
5+ YOEU.S. citizen with 3–8+ years FPGA/RTL verification experience, proficiency with VUnit and HDL (SystemVerilog/Verilog/VHDL), ability to obtain DoD Secret/Top-Secret clearance, and degree in EE/CE/CS or related field.
VUnit, SystemVerilog, Verilog, VHDL, Synopsys, Mentor Graphics, Bash, Perl, Python, Tcl, Makefile, Xilinx, MicroChip
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Lead ASIC Digital Design Engineer
Annapolis Junction or Boise or Salt Lake City or Bloomington or United States
$177k-$187k/yr RemoteFull Time
8+ YOEBachelor's in ECE or related plus 8+ years (or Master's plus 6+ years), strong RTL/ASIC/FPGA design experience, ASIC tape-out and timing closure experience, ability to obtain DoD Secret clearance, proficiency with JIRA and Microsoft Office.
JIRA, Microsoft Office
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Sr. FPGA Developer (Hybrid- Aberdeen Proving Ground, Maryland)
Aberdeen Proving Ground or Middletown
$150k-$175k/yr HybridFull Time
10+ YOEBachelor's in EE/CE,10+ years FPGA design experience with Xilinx Vivado, Verilog/VHDL, RFSoC/Versal platforms, RTL-to-hardware validation, AXI interfaces, and eligibility for DoD Secret clearance.
Xilinx Vivado, Verilog, VHDL, Siemens Questa, Vivado Simulator, Xilinx Zynq UltraScale+ RFSoC, Zynq UltraScale+ MPSoC, Versal, Versal ACAP, ADRV9009, AD9081, ADRV9009-ZU11EG, AXI-Lite, AXI-Stream, JESD204B, JESD204C, JTAG, Integrated Logic Analyzer (ILA), VIO, Ethernet, PCIe, Tcl, Python
6d
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PrProServe Account Executive , NAMER RTL/CPG
Arlington or Chicago or Dallas
$170k-$230k/yr OnsiteFull Time
7+ YOE7+ years B2B/enterprise services sales experience, consultative selling to C-level, experience with large commercial deals, bachelor's in computer science/engineering or equivalent, strong analytics and negotiation skills.
AWS services, CRM systems
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Engineering and Physical Sciences Researcher- Mid to Experienced Level (Maryland)
Fort Meade, Maryland, United States
$105k-$193k/yr OnsiteFull Time
3+ YOEDegree in engineering, physics/astronomy, or related technical field; relevant research or engineering experience; publication and collaboration record; demonstrated technical skills in device/ASIC/architecture research.
Verilog, RTL, FPGA, Cadence, Synopsys