51 rtl engineer jobs at 10 companies in Wilmer, TX
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RTL Design Engineer
Richardson, Texas, United States
HybridFull Time
Bachelor’s or master’s degree in engineering; experienced Verilog/SystemVerilog RTL designer with ASIC/SoC flows, synthesis, verification debug, EDA tools, and cross-functional IC development experience.
Verilog, SystemVerilog, ASIC, SoC, Electronic Design Automation (EDA), CDC, APR
3mo
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HBM SoC RTL Design Engineer
Folsom or Richardson
$146k-$297k/yr OnsiteFull Time
10+ YOEBachelor's or master's in EE/CE (required) with 10+ years' experience; proficiency in SystemVerilog/Verilog, SoC integration, RTL-to-GDS flow, EDA tools (Cadence/Synopsys/Siemens), and scripting (Python, TCL, Perl, shell).
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Python, TCL, Perl, Shell, Palladium, Veloce, Zebu
2mo
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Staff Design Verification Engineer, HBM Architecture
Richardson, Texas, United States
OnsiteFull Time
7+ YOEBachelor's in EE/CE, 7+ years verification engineering experience (including 5+ years in digital/analog/mixed-signal), 4+ years custom or RTL verification, strong communication and independent verification strategy skills.
Verilog, FastSpice, GenAI, RTL
4d
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Hardware Electronics Engineer
Richardson, Texas, United States
$91k-$133k/yr OnsiteFull Time
5+ YOEBachelor's degree in Electrical Engineering; 5+ years of Verilog HDL programming; FPGA, SERDES, DDR3/DDR4, embedded processor, RTL simulation, PCB, and Linux experience preferred or required.
Verilog HDL, Altera, AMD, Xilinx, SERDES, DDR3, DDR4, Xilinx Zynq SoC, Questa Simulator, Linux, AVB
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Hardware Electronics Engineer
Richardson, Texas, United States
$91k-$133k/yr OnsiteFull Time
5+ YOEBachelor's degree in electrical engineering, 5+ years of Verilog HDL experience, FPGA development with Altera and AMD Xilinx devices, RTL simulation, and FPGA memory and processor interface experience.
Verilog HDL, FPGA, Altera, AMD, Xilinx, SERDES, DDR3, DDR4, Xilinx Zynq SoC, Questa Simulator, Linux
3d
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Staff Engineer AI/ML
Santa Clara or Richardson or Austin
$143k-$275k/yr OnsiteFull Time
5+ YOEMaster's with 10+ years or PhD with 5+ years; processor, microarchitecture, datapath, RTL, SystemVerilog, Verilog/VHDL, simulation, waveform debugging, timing, and power expertise required.
RISC-V, SystemVerilog, Verilog, VHDL, Perl, Python
2mo
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Digital IC Design Engineer | Custom
Dallas, Texas, United States
OnsiteFull Time
8+ YOEBachelor's in EE/ECE/Computer Engineering, 8 years engineering experience including 3 years mixed-signal design verification, experience with Gates+SDF timing verification, automation scripting, and mixed-signal verification flows.
JasperGold, Gates+SDF, RTL, STA
3d
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Staff Engineer AI/ML
Santa Clara or Austin or Richardson
$143k-$275k/yr OnsiteFull Time
10+ YOEMaster's with 10+ years or PhD with 5+ years; expertise in CPU, vector or GPU architecture, RTL, SystemVerilog, Verilog or VHDL, microarchitecture, datapaths, verification, timing, power, and area.
SystemVerilog, Verilog, VHDL, Perl, Python, RISC-V, ARM, MIPS, GPUs, SIMD
4w
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Senior Staff Digital Design Engineer
Plano, Texas, United States
HybridFull Time
5+ YOE5+ years in digital IC design with Verilog/SystemVerilog, RTL, synthesis, STA, verification, silicon debug, UVM and experience with industry EDA tools; B.Tech/M.Tech in electronics or related field.
Verilog/SystemVerilog, UVM, I²C, I3C, SPI, UART, Python, Tcl, Perl, Shell, Xcelium, Genus, SpyGlass, OneSpin/JasperGold, Innovus, PrimeTime/Tempus, DFT, ARM, AMBA (AXI/AHB/APB), Cadence Virtuoso, STA, LEC, Lint, Formal Verification
2mo
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Principal Engineer, Digital Design (IO Subsystem)
Allen, Texas, United States
OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
10+ YOEBachelor's in EE (Master's preferred), 10+ years digital IC/RTL design, expert SystemVerilog, Python, UVM, UPF/STA/timing signoff, DFT experience, and strong cross-functional collaboration.
SystemVerilog, Python, UVM, UPF, STA, DFT, AI/ML
3w
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Senior ASIC/FPGA Design Engineer
McKinney, Texas, United States
$87k-$165k/yr OnsiteFull Time
5+ YOEBachelor's in STEM,5+ years FPGA/ASIC design and RTL experience,experience with Xilinx/Altera and high-speed interfaces,Python/Perl/Shell scripting,ability to obtain U.S. government security clearance;U.S. citizenship required.
Xilinx, Altera, Python, Perl, Shell, System Verilog, UVM, MATLAB, PCI/PCIe, VPX, Gb Ethernet, Ienterlaken
2mo
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Principal Engineer DSP PHY Digital Design
Dallas, Texas, United States
HybridFull Time
10+ YOEB.S. +10 yrs or M.S. +7 yrs in EE/CE or related; strong digital communications/DSP fundamentals; experience with high-speed wireline DSP (FFE/DFE, CDR, FEC), RTL design/verification; C++, MATLAB proficiency.
C++, MATLAB, Python
2mo
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Staff Wireless IC Digital Designer
Dallas, Texas, United States
OnsiteFull Time
8+ YOESenior level design engineer with 8-12 years in digital RF/wireless design, IC/SoC development, RTL, and verification.
RTL, Synthesis, STA, ATPG, RFIC, SoC, Digital design, FPGA design
2mo
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Full Stack Engineer (Delivery Toolkit)
Atlanta or Austin or Chicago or Dallas or Houston
$93k-$112k/yr HybridFull Time
2+ YOEBachelor's degree or equivalent; 2+ years building web or backend services; strong TypeScript, Node.js, FastAPI/Python, SQL/Postgres, testing, and practical AWS experience; familiarity with CI/CD, Docker, and IaC.
Svelte, SvelteKit, React, TypeScript, Node.js, Python, FastAPI, Zod, Pydantic v2, PostgreSQL, SQL, SQLAlchemy, Docker, Vitest, RTL, Jest, pytest, Playwright, OpenAPI, GitHub Actions, Cursor, GitHub Copilot, S3, RDS, Lambda, ECS, CloudWatch, IAM, API Gateway, SQS, SNS, EventBridge, ECR, Terraform, CloudFormation, CDK
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