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HBM SoC RTL Design Engineer
Folsom, California, United States
$146k-$297k/yr OnsiteFull Time
10+ YOE10+ years in electrical/computer engineering; SystemVerilog/Verilog; RTL-to-GDS flow; Cadence/Synopsys/Siemens; Python/TCL/Perl scripting.
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Python, TCL, Perl
2mo
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HBM SoC RTL Design Engineer
Folsom or Richardson
$146k-$297k/yr OnsiteFull Time
10+ YOEBachelor's or master's in EE/CE (required) with 10+ years' experience; proficiency in SystemVerilog/Verilog, SoC integration, RTL-to-GDS flow, EDA tools (Cadence/Synopsys/Siemens), and scripting (Python, TCL, Perl, shell).
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Python, TCL, Perl, Shell, Palladium, Veloce, Zebu
1mo
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Senior FPGA Engineer - Control Systems
Boulder or Austin or Berkeley
$140k-$175k/yr OnsiteFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
5+ YOESenior FPGA engineer with 5+ years in FPGA/digital design; BS in EE/Physics or related field; strong SystemVerilog, RTL, Xilinx Vivado, Zynq, C/C++, Python; Linux experience; willing to learn quantum concepts.
RTL, SystemVerilog, VHDL, Vivado, Xilinx Zynq, Git, Yocto, C, C++, Python, Linux, Prototyping
2mo
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOEDesign ASICs with Verilog/SystemVerilog, RTL, timing, verification; collaborate with verification and physical design; 5+ years of relevant experience.
Verilog, SystemVerilog, RTL, SVA, EDA tools, Python, Perl
4w
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IP Logic Design Engineer
Rancho Cordova, California, United States
$105k-$165k/yr OnsiteFull Time
7+ YOEMS in ECE with 7+ years or BS with 9+ years; expertise in Verilog/SystemVerilog and ASIC flow (RTL, synthesis, STA, ECO); experience with lint, CDC/RDC analysis, verification tools, scripting, and pre/post-silicon debug; 3D NAND experience preferred.
SystemVerilog, Verilog, RTL, synthesis, Static Timing Analysis (STA), ECO, lint tools, CDC/RDC analysis, SystemVerilog Assertions (SVAs), Gate-level simulation (GLS), Design for Testability (DFT)
2mo
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOE5+ years in ASIC/SoC design with Verilog/SystemVerilog, RTL, timing closure, verification; strong problem-solving and communications.
Verilog, SystemVerilog, EDA tools, Synthesis, SVA, Python, Perl
1mo
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Mixed Signal Logic Design Engineer
Folsom or San Jose or Santa Clara
$122k-$232k/yr OnsiteFull Time
4+ YOEBachelor's with 4+ years or Master's with 3+ years or PhD with 1+ year in CS/CE/EE; 2+ years RTL design SystemVerilog/Verilog; mixed-signal, UPF, clock gating; VCS/Verdi; FE tools; no visa sponsorship.
SystemVerilog, Verilog, VCS, Verdi, UPF, Lint, CDC, RDC, Synthesis, Voltage Domain Crossings, DDR, LPDDR, VSCode, Git
3w
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GPU Performance Architect
Folsom, California, United States
$106k-$183k/yr OnsiteFull Time
Undergraduate degree required. Experience in GPU architecture, performance analysis, AI/ML/graphics algorithms, kernel development (PyTorch, Triton, CUDA, HIP) and strong C/C++/Python skills. Knowledge of DirectX, Vulkan, RTL, profiling tools (PIX, RenderDoc, AMD tools) and simulation models.
PyTorch, Triton, CUDA, HIP, C, C++, Python, DirectX, Vulkan, RTL, RenderDoc, PIX, AMD tools
3mo
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Core Performance Architect
Santa Clara or Hsinchu or Austin or Berkeley
$254k-$311k/yr OnsiteFull Time
10+ YOEMS or PhD in Computer Science or Computer Architecture; 10+ years in high-performance processor development; 5+ years in engineering teams delivering HW/SW products; hands-on HW/RTL/FPGA experience; strong micro-architecture performance analysis; workload characterization expertise.
HW, RTL, FPGA, waveform_debugging, performance_analysis, simulation
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