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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOEDesign ASICs with Verilog/SystemVerilog, RTL, timing, verification; collaborate with verification and physical design; 5+ years of relevant experience.
Verilog, SystemVerilog, RTL, SVA, EDA tools, Python, Perl
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOEBachelor’s in Electrical Engineering; 5+ years ASIC design experience; strong Verilog/SystemVerilog; timing/room for leadership; knowledge of EDA tools; Python/Perl a plus.
Verilog, SystemVerilog, EDA tools, Python, Perl
2mo
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOE5+ years in ASIC/SoC design with Verilog/SystemVerilog, RTL, timing closure, verification; strong problem-solving and communications.
Verilog, SystemVerilog, EDA tools, Synthesis, SVA, Python, Perl
1mo
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Staff Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
6+ YOEBS in electrical engineering or computer science; 6-8 years verification; RTL debugging, scoreboarding, and code coverage; test plans and coverage definitions.
SystemVerilog, UVM, C, DDR, PCIe/NVMe, NAND
1mo
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Staff/Principal Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
6+ YOEB.S. in EE/CS or equivalent, 6+ years verification experience, RTL debugging, scoreboarding, code coverage analysis, test-plan development; System-Verilog/UVM expertise preferred; familiarity with C and emulation advantageous.
System-Verilog, UVM, C, Claude-Code, RTL
3w
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Manufacturing Engineer, Advanced
Santa Rosa, California, United States
$101k-$168k/yr OnsiteFull Time
7+ YOEBSEE or MSEE; 7+ years manufacturing engineering experience with high-speed electrical components; CPI/Lean and Six Sigma experience; ASIC failure analysis; strong RF fundamentals.
Continuous Process Improvement (CPI), Lean, Six Sigma
3mo
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Technical Staff Engineer - Emulation
San Jose or Roseville
$91k-$232k/yr OnsiteFull Time
12+ YOEBachelor's in Electrical or Computer Engineering; 12+ years in ASIC development and emulation; strong problem solving and communication; experience with PCIe, Cadence Palladium/Protium; UVM testbenches; SoC emulation expertise.
Cadence Palladium, Cadence Protium, PCIe, DDR, ONFI, AMBA AXI, SAS, NVMe, UVM, BFM, C
3mo
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Power Infrastructure Engineer
Santa Clara or Berkeley or Austin or Bengaluru or Hsinchu
$206k-$251k/yr OnsiteFull Time
5+ YOEMS or PhD in Computer Science or Computer Architecture; 5+ years in power benchmarking, analysis, and modeling; experience with ASIC power analysis; hardware/software integration; ability to balance performance and power.
1w
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IC Design Engineer
Berkeley, California, United States
$111k-$223k/yr OnsiteFull Time
2+ YOEDesign and develop high-performance analog/mixed-signal ASICs, perform block design, layout, verification, test and chip integration; collaborate with scientific teams; proficiency with IC design suites and simulators.
Cadence, Spectre, Eldo, HSPICE, FPGA, Verilog, VHDL, PDK
1w
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IC Design Engineer
Berkeley, California, United States
$125k-$182k/yr OnsiteFull Time
2+ YOE2+ years IC design experience (Level 2) or equivalent advanced degree; strong analog/mixed-signal design skills; proficiency with Cadence and transistor-level simulators; ability to design, test, and integrate ASICs for scientific instruments.
Cadence, Spectre, Eldo, HSPICE, Verilog, VHDL, FPGA, PDK
4w
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IP Logic Design Engineer
Rancho Cordova, California, United States
$105k-$165k/yr OnsiteFull Time
7+ YOEMS in ECE with 7+ years or BS with 9+ years; expertise in Verilog/SystemVerilog and ASIC flow (RTL, synthesis, STA, ECO); experience with lint, CDC/RDC analysis, verification tools, scripting, and pre/post-silicon debug; 3D NAND experience preferred.
SystemVerilog, Verilog, RTL, synthesis, Static Timing Analysis (STA), ECO, lint tools, CDC/RDC analysis, SystemVerilog Assertions (SVAs), Gate-level simulation (GLS), Design for Testability (DFT)
3w
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Senior Technologist, Hardware Development Engineering -
Roseville, California, United States
$177k-$235k/yr OnsiteFull Time
Expert-level hardware engineer with hands-on board and ASIC integration experience, high-speed interface and SI/PI expertise, lab bring-up and root-cause debug, and cross-functional technical leadership.
Cadence, Altium, Mentor, IBIS, AMI, S-parameters, SPICE, Oscilloscope, BERT, Network Analyzer, Spectrum Analyzer, JTAG, PRBS, IBERT
1mo
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Senior SoC Network Subsystem Architect
Santa Clara or Hillsboro or Folsom or Austin or Phoenix or San Jose
$164k-$269k/yr HybridFull Time
7+ YOEBachelor's in EE/CE/CS and 7+ years building networking ASIC/SoC/IPU/DPU architectures, high-speed packet processing pipelines, and system-level tradeoffs; experience with programmable datapaths (P4) preferred.
P4
1w
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Principal SoC Architect
Walnut Creek, California, United States
$168k-$300k/yr OnsiteFull Time
12+ YOEBachelor's in EE/CE,12+ years ARM CPU SoC/ASIC architecture experience, Ethernet/PCIe and memory subsystem expertise, EM/thermal tradeoff and IP selection experience, scripting in Tcl/Perl/Python preferred.
Tcl, Perl, Python
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