4w
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RTL Design/AMS Verification Engineer
Richardson, Texas, United States
RemoteFull Time
5+ YOE5+ years IC design experience; Verilog RTL design and verification experience; Cadence/Synopsys flows; AMS simulation, synthesis and APR; Bachelor's degree in Electrical Engineering; US work authorization (ITAR) required.
Verilog, Cadence, Synopsys, Python, Perl, Tcl, SKILL
1mo
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Staff Design Verification Engineer, HBM Architecture
Richardson, Texas, United States
OnsiteFull Time
7+ YOEBachelor's in EE/CE, 7+ years verification engineering experience (including 5+ years in digital/analog/mixed-signal), 4+ years custom or RTL verification, strong communication and independent verification strategy skills.
Verilog, FastSpice, GenAI, RTL
2mo
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Sr Design Verification Engineer/Architect, HBM
Richardson, Texas, United States
OnsiteFull Time
4+ YOEBachelor's degree in Electrical or Computer Engineering; 4+ years verification experience; strong in digital, analog, or mixed-signal verification; 2+ years in custom RTL/design verification.
Verilog, FastSpice, Co-simulation
1w
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Mixed-Signal Design Verification Engineer | Custom
Dallas, Texas, United States
OnsiteFull Time
8+ YOE8+ years design verification experience with 4+ years on high-speed clock/data paths; strong mixed-signal and digital verification, analog and digital design knowledge, timing verification, and scripting/automation skills.
Verilog, SystemVerilog, Verilog-AMS, Cadence Virtuoso, Spectre, Simvision, Starfish, CDDS, RTL
3mo
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Staff Engineer, HBM Verification Architecture
Richardson, Texas, United States
OnsiteFull Time
7+ YOE7+ years in verification engineering; experience in digital, analog, and mixed-signal verification; strong communication; independence in defining verification strategies.
Verilog, FastSpice, RTL, GenAI
2mo
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Senior Engineer, Digital Design Engineering
Dallas, Texas, United States
$124k-$175k/yr HybridFull Time
2+ YOEMaster’s degree in Electrical/Electronic Engineering or Computer Science/Engineering; 2+ years in digital design or related; RTL design, verification, and CAD tools experience.
Verilog, SystemVerilog, Cadence, Synopsys, RTL, Synthesis, Simulation, Lint, CDC
1mo
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DFT Engineer (Design for Testability) - Staff
Richardson, Texas, United States
OnsiteFull Time
5+ YOEBachelor's/Master's in EE/CE or equivalent, strong digital design and DFT fundamentals (scan, MBIST, JTAG), RTL experience (SystemVerilog/VHDL), familiarity with semiconductor test flows, and 5+ years DRAM or ASIC DFT design/verification experience.
SystemVerilog, VHDL, RTL, JTAG, MBIST
1mo
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Digital IC Design Engineer | Custom
Dallas, Texas, United States
OnsiteFull Time
8+ YOEBachelor's in EE/ECE/Computer Engineering, 8 years engineering experience including 3 years mixed-signal design verification, experience with Gates+SDF timing verification, automation scripting, and mixed-signal verification flows.
JasperGold, Gates+SDF, RTL, STA
1w
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Senior Staff Digital Design Engineer
Plano, Texas, United States
HybridFull Time
5+ YOE5+ years in digital IC design with Verilog/SystemVerilog, RTL, synthesis, STA, verification, silicon debug, UVM and experience with industry EDA tools; B.Tech/M.Tech in electronics or related field.
Verilog/SystemVerilog, UVM, I²C, I3C, SPI, UART, Python, Tcl, Perl, Shell, Xcelium, Genus, SpyGlass, OneSpin/JasperGold, Innovus, PrimeTime/Tempus, DFT, ARM, AMBA (AXI/AHB/APB), Cadence Virtuoso, STA, LEC, Lint, Formal Verification
2mo
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Non-Volatile Memory Circuit Design Engineer
Richardson, Texas, United States
RemoteFull Time
10+ YOE10+ years NVM circuit design experience; Cadence/Synopsys flow; RTL design/verification; EE degree; remote option depending on skills.
Cadence, Synopsys, RTL design tools, PERL, Python, TCL, SKILL
1mo
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Digital IC Design Engineer
Dallas, Texas, United States
OnsiteFull Time
1+ YOEBachelor's in EE/CE or related; 1+ years digital IC design experience; proficiency in RTL (Verilog/SystemVerilog), functional verification, synthesis/static timing, low-power techniques; exposure to SPI/I2C/UART; scripting (Python, Tcl, Perl).
Verilog, SystemVerilog, Synopsys Design Compiler, Cadence Genus, Python, Tcl, Perl
1mo
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Principal Engineer DSP PHY Digital Design
Dallas, Texas, United States
HybridFull Time
10+ YOEB.S. +10 yrs or M.S. +7 yrs in EE/CE or related; strong digital communications/DSP fundamentals; experience with high-speed wireline DSP (FFE/DFE, CDR, FEC), RTL design/verification; C++, MATLAB proficiency.
C++, MATLAB, Python
2mo
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Staff Wireless IC Digital Designer
Dallas, Texas, United States
OnsiteFull Time
8+ YOESenior level design engineer with 8-12 years in digital RF/wireless design, IC/SoC development, RTL, and verification.
RTL, Synthesis, STA, ATPG, RFIC, SoC, Digital design, FPGA design