2mo
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SoC Design Engineer
Austin, Texas, United States
$122k-$232k/yr HybridFull Time
3+ YOEBachelor's in Electrical/Computer Engineering; 3+ years in microarchitecture/RTL design; clock domain crossing, low-power design; RTL tools, SoC integration.
RTL design, SoC integration tools, NoC architectures, Low-power design, Power-area-timing optimization
3mo
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SoC Design Engineer
Santa Clara, California, United States
$157k-$160k/yr OnsiteFull Time
Master’s in Electrical or Computer Engineering; ASIC/SoC design experience; RTL/verification; EDA tools; programming (Python/C++/Perl).
Verilog, SystemVerilog, PrimeTime, Cadence Virtuoso, Design Compiler, Simvision, Python, C++, Perl, SVA, HLS, EDA Tools
1mo
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Senior SOC Design Engineer
Santa Clara, California, United States
$136k-$265k/yr HybridFull Time
3+ YOEBS/MS in Computer or Electrical Engineering (or equivalent), 3+ years chip design experience focused on SoC integration and automation; expertise in RTL, SOC integration, design automation; scripting with Perl or Python; strong analytical and communication skills.
Perl, Python, RTL, EDA tools
1mo
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SoC Design Engineer
United States
$150k-$175k/yr RemoteFull Time
5+ YOE5+ years semiconductor engineering with leadership across analog, digital (RTL), mixed-signal, and physical implementation; proven SoC/ASIC tape-out and silicon bring-up experience; B.S. in ECE or equivalent; strong operational and communication skills.
RTL, DFT, CAD, UCIe
2mo
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Wireless SoC Design Engineer
San Diego or Sunnyvale
OnsiteFull Time
Bachelor's degree in Electrical Engineering or Computer Engineering; experience with ASIC/SoC RTL design; SystemVerilog; cross-functional collaboration.
SystemVerilog, SystemVerilog RTL, Synthesis, STA, Lint, CDC, RDC, DFT, DFT, PCIe, QSPI, UART, SPMI
2mo
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SOC Silicon Design Engineer
Austin or Boxborough
HybridFull Time
Design and develop custom silicon for CG SoC; collaborate across teams; strong analytical and communication skills.
Scripting (Perl, TCL, Python), EDA tools, VLSI design flow, CMOS technology
3d
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Principal Engineer, SOC Design
Folsom, California, United States
$199k-$319k/yr OnsiteFull Time
15+ YOEExtensive SoC architecture and RTL development experience with modern DRAM technologies, verification/debugging skills, FPGA prototyping or silicon bring-up experience, and strong technical leadership.
SystemVerilog, Verilog, FPGA
3d
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Senior SoC/RTL Design Engineer
San Diego, California, United States
$129k-$173k/yr OnsiteFull Time
Design, implement, and verify digital architecture and Verilog RTL for complex ASIC/SoC, perform board design and circuit debug, and collaborate with cross-functional teams.
Verilog
2mo
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Senior SOC Physical Design Engineer, HBM
Richardson, Texas, United States
OnsiteFull Time
3+ YOESenior SOC physical design engineer with hands-on experience in EDA tools, timing, power intent, DFT/MBIST, and HBM-based SoC integration.
Innovus, Fusion Compiler, IC Validator, Calibre, PrimeTime, Tempus, Synopsys Design Constraints, UPF, CPF, Ansys, Tcl, Python
2w
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Lead SoC Design Engineer
Los Altos, California, United States
OnsiteFull Time
Anodize: Developing next-generation personal computing hardware and consumer electronics.
10+ YOE10+ years developing complex ASICs; Bachelor's in EE/CE (or equivalent); deep knowledge of AMBA protocols, Verilog/SystemVerilog/SVA, SDC timing constraints, multi-power-domain design and UPF; experience with ASIC CAD flows.
AMBA AXI, AXI-S, APB, Verilog, SystemVerilog, SystemVerilog Assertions (SVA), SDC, STA, Lint, CDC, RDC, LEC, UPF, UCIe, DDR, Arm
1mo
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HBM SoC Physical Design Engineer
Richardson, Texas, United States
OnsiteFull Time
10+ YOEHands-on SoC physical design from netlist to GDSII on advanced nodes; proficiency with industry EDA tools, STA/SDC, power intent (UPF/CPF), physical verification, and strong timing/power optimization skills.
Cadence Innovus, Cadence Tempus, Synopsys ICC2, Synopsys PrimeTime, Siemens Calibre, GDSII, SDC, UPF, CPF
1mo
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SoC RTL Design Engineer
San Jose or Bangalore
HybridFull Time
8+ YOEBS/MS in Electrical or Computer Engineering; 8+ years in digital IC design with chip infrastructure ownership (clocking, power management, reset/DFT) at block-lead or subsystem level; strong SystemVerilog and infrastructure RTL skills; experience with embedded microcontroller integration and security features.
SystemVerilog, RTL Design, Power Management, Clock Gating, Reset, DFT, BIST, Interrupt Controller, UART, JTAG, PCIe, UCIe
4d
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TPU SoC Design Engineer, Google Cloud
Sunnyvale, California, United States
$116k-$166k/yr OnsiteFull Time
2+ YOEBachelor's degree or equivalent,2+ years ASIC RTL design with SystemVerilog/Verilog,experience with EDA tools,knowledge of digital design,EMR not required,excellent communication and critical thinking.
SystemVerilog, Verilog, Python, Tcl, Perl, Verdi, VCS, AXI, CDC, UPF, RDC, LEC
3mo
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Design Verification Engineer - SoC
San Jose, California, United States
$150k-$275k/yr OnsiteFull Time
Design verification for ASIC/SoC; SystemVerilog and Python; performance modeling; test benches and verification infrastructure.
SystemVerilog, Python
2mo
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Senior Staff SoC Design Engineer
Santa Clara, California, United States
$134k-$201k/yr OnsiteFull Time
5+ YOEBachelor's in CS/EE with 5-10 years; or Master's/PhD with 3-5 years; strong SystemVerilog RTL; SoC integration; AMBA AXI; scripting (Python/Tcl).
SystemVerilog, AMBA AXI, Python, Tcl, Synthesis, CDC/RDC, UCIe, UALink
2w
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Senior SoC Digital Design Engineer, Multimedia Lab
San Jose, California, United States
$213k-$450k/yr OnsiteFull Time
3+ YOEBachelor's in EE/CS or related, 3+ years front-end digital/SoC design, mastery of Verilog/SystemVerilog, experience with front-end EDA tools, scripting (Python/Perl/Tcl/Makefile), and low-power design techniques.
Verilog, SystemVerilog, Spyglass, Design Compiler, PrimeTime, Python, Perl, Tcl, Makefile, UPF, SDC, STA
1mo
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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine or Austin or Sunnyvale
$160k-$220k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical engineering, computer engineering or computer science; 5+ years ASIC/physical design experience; strong EDA tool knowledge; scripting skills; ability to work extended hours.
EDA tools, Python, Csh/Bash/Shell, Perl, TCL, Makefile
5d
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SoC Design Verification Engineer (2026 New College Graduate)
Richardson, Texas, United States
$86k-$148k/yr OnsiteFull Time
0+ YOEBachelor's in EE/CE or related, 0-2 years digital verification experience, Verilog/SystemVerilog, Python/Tcl/Perl, UNIX/EDA tools, strong analytical and communication skills.
Verilog, SystemVerilog, Python, Tcl/Tk, Perl, UNIX, EDA design tools, RISC-V, ARM, MIPS, C, C++
5d
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SoC Design Verification Engineer (2026 New College Graduate)
Richardson, Texas, United States
$86k-$148k/yr OnsiteFull Time
0+ YOEBachelor's in EE/CE,0-2 years digital verification experience, proficiency with Verilog/SystemVerilog, scripting (Python,Tcl/Tk,Perl), UNIX and EDA tools, strong analytical and communication skills.
Verilog, SystemVerilog, Python, Tcl/Tk, Perl, C, C++, UNIX, EDA design tools
1mo
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Principal IC SoC Integration and Design Engineer
Mendota Heights or Fort Collins or Broomfield
$129k-$207k/yr OnsiteFull Time
10+ YOEBachelor's (EE/CE/CS) +12 yrs or Master's +10 yrs; expertise in Verilog/VHDL/SystemVerilog, AMBA, high-speed SERDES/DRAM interfaces, physical implementation and timing closure; strong communication and collaboration; US work authorization required.
AMBA, UART, DRAM, SERDES, Verilog, VHDL, SystemVerilog
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