284 soc design jobs at 75 companies in San Jose, CA
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Senior SOC Design Engineer
Santa Clara, California, United States
$136k-$265k/yr HybridFull Time
3+ YOEBS/MS in Computer or Electrical Engineering (or equivalent), 3+ years chip design experience focused on SoC integration and automation; expertise in RTL, SOC integration, design automation; scripting with Perl or Python; strong analytical and communication skills.
Perl, Python, RTL, EDA tools
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SoC Design Engineer
Santa Clara, California, United States
$157k-$160k/yr OnsiteFull Time
1+ YOEMaster's in Electrical or Computer Engineering required, 1+ year digital design experience; RTL/Verilog, SystemVerilog/SVA, Python, Perl; experience with Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator; FPGA prototyping, STA, DFT.
Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator, SystemVerilog, SVA, Python, Perl, Verilog, FPGA
4w
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SoC Logic Design Engineer
Austin or Santa Clara or Hillsboro
$142k-$200k/yr HybridFull Time
3+ YOEExperience in RTL/Verilog logic design, SoC integration, low-power and timing optimization, Clock Domain Crossing and NoC architectures, AMBA protocols; bachelor's or master's in EE/CE with relevant years of experience.
RTL, Verilog, AMBA, CHI, AXI, AHB, APB, Network-on-Chip (NoC), Clock Domain Crossing
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SoC Machine Learning Design Engineer
Cupertino, California, United States
OnsiteFull Time
Expertise in machine learning applied to SoC design and validation; ability to collaborate with cross-functional teams to improve productivity and optimizations across SoC design functions.
1w
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Senior SoC/RTL Design Engineer
Santa Clara, California, United States
$147k-$190k/yr OnsiteFull Time
Master's degree in electrical, computer, or related engineering field; experience independently planning, designing, coding, implementing, and verifying complex digital ASICs and SoCs.
Verilog, System on Chip (SoC), RTL
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Lead SoC Design Engineer
Los Altos, California, United States
OnsiteFull Time
Anodize: Developing next-generation personal computing hardware and consumer electronics.
10+ YOE10+ years developing complex ASICs; Bachelor's in EE/CE (or equivalent); deep knowledge of AMBA protocols, Verilog/SystemVerilog/SVA, SDC timing constraints, multi-power-domain design and UPF; experience with ASIC CAD flows.
AMBA AXI, AXI-S, APB, Verilog, SystemVerilog, SystemVerilog Assertions (SVA), SDC, STA, Lint, CDC, RDC, LEC, UPF, UCIe, DDR, Arm
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Senior SoC Digital Design Engineer, Multimedia Lab
San Jose, California, United States
$213k-$450k/yr OnsiteFull Time
3+ YOEBachelor's in EE/CS or related, 3+ years front-end digital/SoC design, mastery of Verilog/SystemVerilog, experience with front-end EDA tools, scripting (Python/Perl/Tcl/Makefile), and low-power design techniques.
Verilog, SystemVerilog, Spyglass, Design Compiler, PrimeTime, Python, Perl, Tcl, Makefile, UPF, SDC, STA
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SoC RTL Design Engineer
San Jose or Bangalore
HybridFull Time
8+ YOEBS/MS in Electrical or Computer Engineering; 8+ years in digital IC design with chip infrastructure ownership (clocking, power management, reset/DFT) at block-lead or subsystem level; strong SystemVerilog and infrastructure RTL skills; experience with embedded microcontroller integration and security features.
SystemVerilog, RTL Design, Power Management, Clock Gating, Reset, DFT, BIST, Interrupt Controller, UART, JTAG, PCIe, UCIe
4w
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TPU SoC Design Engineer, Google Cloud
Sunnyvale, California, United States
$116k-$166k/yr OnsiteFull Time
2+ YOEBachelor's degree or equivalent,2+ years ASIC RTL design with SystemVerilog/Verilog,experience with EDA tools,knowledge of digital design,EMR not required,excellent communication and critical thinking.
SystemVerilog, Verilog, Python, Tcl, Perl, Verdi, VCS, AXI, CDC, UPF, RDC, LEC
2w
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SoC Architect
Mountain View, California, United States
$251k-$310k/yr HybridFull Time
10+ YOEMS or equivalent,10+ years ASIC/SoC digital design and microarchitecture experience, ownership of major design blocks and successful tapeouts, SystemVerilog expertise, Python/C++ fluency, strong debug and leadership skills.
SystemVerilog, Python, C++, Chisel (Scala)
3w
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SoC Design Verification Engineer
San Jose, California, United States
$124k-$213k/yr HybridFull Time
Experience in SoC/CPU verification, testbench development, and verification metrics; strong coding in Verilog/System Verilog, UVM, C/C++, scripting (Perl/Python); Bachelors/Masters in computer or electrical engineering.
Verilog, System Verilog, UVM, C, C++, Perl, Python
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Physical Design - SOC Top Lead
San Jose or Pittsburgh or Austin
$200k-$250k/yr OnsiteFull Time
8+ YOEEnd-to-end SOC top ownership including full-chip integration, timing closure, power/PDN analysis, physical verification, SI, clock/reset, DFT, package co-design, and tapeout readiness; advanced degree in EE and extensive PD experience.
Innovus, ICC2, Tempus, PrimeTime, RedHawk, Calibre, Voltus, TCL, shell, python
1w
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Staff Design Verification Engineer – SoC and eFPGA
San Jose, California, United States
$151k-$219k/yr OnsiteFull Time
5+ YOEMaster's degree or equivalent experience; expertise in SoC verification, UVM, SystemVerilog, Verilog, C/C++, Python, RTL debugging, bus protocols, automation, and distributed compute environments.
UVM, SystemVerilog, Verilog, C, C++, Python, SystemC, Transaction-Level Modeling (TLM), AXI, AHB, RTL, FPGA, SoC
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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine or Austin or Sunnyvale
$160k-$220k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical engineering, computer engineering or computer science; 5+ years ASIC/physical design experience; strong EDA tool knowledge; scripting skills; ability to work extended hours.
EDA tools, Python, Csh/Bash/Shell, Perl, TCL, Makefile
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Staff SoC RTL Engineer
Burlingame, California, United States
$175k-$230k/yr HybridFull Time
5+ YOEBS, MS, or Ph.D. in electrical or computer engineering; 5+ years of SoC/ASIC front-end design and integration; SystemVerilog or Verilog; computer architecture, low-power design, subsystem, and VCS experience.
SystemVerilog, Verilog, VCS, C++, FPGA
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SoC Interconnect Technology Team Lead
San Jose, California, United States
$398k-$538k/yr HybridFull Time
15+ YOE15+ years SoC architecture/design experience with interconnects, deep knowledge of coherent and non-coherent protocols, performance modeling, and proven leadership delivering complex SoCs to tape-out.
AMBA ACE, AMBA CHI, CCIX, CXL, AXI, NoC
3mo
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Staff/Principal Engineer - Design Verification (SoC expert/lead)
San Jose, California, United States
$168k-$336k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CS or equivalent, 10+ years SoC verification experience, expert SystemVerilog and UVM, experience developing SoC test plans, emulation exposure, and leadership in complex verification programs.
SystemVerilog, UVM, Gen-AI
3mo
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Sr. Principal SoC Architect (AI2501)
San Jose, California, United States
$231k-$358k/yr OnsiteFull Time
20+ YOEMS or PhD in EE/CS, 20+ years developing hardware-focused products, 3+ years architecting and tape-out of complex ML SoCs, strong ML/math foundation, HW/SW co-design and industry/publication experience.
1mo
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SoC Product Architect, Memory Ecosystem
Santa Clara, California, United States
$320k-$489k/yr OnsiteFull Time
18+ YOEMS in EE/CE/Physics or equivalent experience; 18+ years in DRAM/memory subsystem architecture or SoC/memory controller design; deep knowledge of DRAM and NVM; experience engaging memory vendors; strong system memory and competitive-analysis skills.
3mo
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SoC Power Architecture Engineer - Processor Subsystem
Saratoga, California, United States
$150k-$220k/yr OnsiteFull Time
7+ YOE7+ years ASIC/SoC low-power design; power domain architecture; UPF; SystemVerilog/VHDL; energy-efficient IoT focus.
UPF (IEEE 1801), SystemVerilog, VHDL, AMBA, Synopsys PrimeTime PX, Cadence Joules
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