3mo
Save
Mark Applied
Hide
SoC Test Engineer
Austin or Cupertino or San Diego
OnsiteFull Time
10+ YOEBachelor's degree and 10+ years in SoC test engineering with strong programming and hardware test skills.
Teradyne UFlex, ip750, J750, Advantest 93k, Oscilloscope, Logic analyzer, PERL, C/C++, Visual Basic
2mo
Save
Mark Applied
Hide
SoC Design Engineer
Santa Clara, California, United States
$157k-$160k/yr OnsiteFull Time
Master’s in Electrical or Computer Engineering; ASIC/SoC design experience; RTL/verification; EDA tools; programming (Python/C++/Perl).
Verilog, SystemVerilog, PrimeTime, Cadence Virtuoso, Design Compiler, Simvision, Python, C++, Perl, SVA, HLS, EDA Tools
1mo
Save
Mark Applied
Hide
Senior SOC Design Engineer
Santa Clara, California, United States
$136k-$265k/yr HybridFull Time
3+ YOEBS/MS in Computer or Electrical Engineering (or equivalent), 3+ years chip design experience focused on SoC integration and automation; expertise in RTL, SOC integration, design automation; scripting with Perl or Python; strong analytical and communication skills.
Perl, Python, RTL, EDA tools
2mo
Save
Mark Applied
Hide
SoC Platform Engineer
Saratoga, California, United States
$150k-$220k/yr OnsiteFull Time
Experience with IP integration, system verification, firmware for SoC; RTL, AMBA interconnects; C/Python scripting; ARM architecture.
SystemVerilog, VHDL, UVM, C, Python, Tcl, Bash, Makefiles, Git, VCS, Questa, Xcelium, JTAG
1mo
Save
Mark Applied
Hide
SOC Intergration Engineer
Mountain View, California, United States
$120k-$600k/yr HybridFull Time
SystemVerilog; Python/Perl; experience integrating CPUs/GPUs/accelerators; SOC RTL; timing constraints; DV automation; emulation/verification familiarity.
SystemVerilog, Python, Perl, RTL design, DV tooling, Synthesis
2w
Save
Mark Applied
Hide
Senior SoC Verification Engineer
Redmond or Austin or Hillsboro or Raleigh or Mountain View
$120k-$235k/yr HybridFull Time
5+ YOEDegree in EE/CE/CS (or equivalent) with 1–5+ years technical engineering experience depending on degree; experience in SoC/ASIC verification, C/C++ testbenches, firmware, silicon bring-up, and scripting (Python/Ruby/Perl). Security/export screening required.
C, C++, Python, Ruby, Perl, UVM, FPGA
1mo
Save
Mark Applied
Hide
SoC Verification Engineer – NoC / UVM
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Expertise in SystemVerilog and UVM, ASIC/SoC verification, constraint-random and coverage-driven methodologies, formal verification (SVA); experience with Synopsys VCS and Cadence IES preferred; B.S. or M.S. in computer/electrical engineering.
SystemVerilog, UVM, OVM, VMM, Verilog, SystemVerilog Assertions (SVA), Synopsys VCS, Cadence IES, Cadence IEV, Jasper, Synopsys VC-Formal, Magellan
3w
Save
Mark Applied
Hide
SOC IP Methodology Engineer - Custom SOC
Santa Clara or Austin or Hillsboro
$168k-$311k/yr OnsiteFull Time
8+ YOEMasters (8+ yrs) or BS (10+ yrs) with deep RTL-to-GDS methodology and physical design expertise, experience with EDA tool flows, IP ecosystems, customer-facing SOC development, DFT/BIST, synthesis/CTS/power/PNR, and scripting (Python/Perl/Tcl).
RTL-to-GDSII, Cadence, Synopsys, Mentor, Genus, First Encounter, Innovus, Design Compiler, Fusion Compiler, ICC2, PT-SI, Tempus, Redhawk, IP-XACT, Python, Perl, Tcl
3w
Save
Mark Applied
Hide
SoC Logic Design Engineer
Hillsboro or Santa Clara or Austin
$142k-$200k/yr HybridFull Time
3+ YOEDegree in electrical/computer engineering (BS+4 yrs / MS+3 yrs / PhD+6 mo) and experience in RTL/SystemVerilog, SoC logic integration, microarchitecture, timing/power convergence, and simulation; scripting and front-end RTL tools preferred.
Register Transfer Level (RTL), System Verilog, Python, Perl, Lint, CDC, Synthesis, Static Timing Analysis (STA), DFT, DFD, UVM
2w
Save
Mark Applied
Hide
SoC DFT Engineer, Cloud
Sunnyvale, California, United States
$163k-$237k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE/CS or equivalent; 5+ years DFT architecture/implementation/verification for SoCs; silicon bring-up and test methodology experience (ATE, MBIST, JTAG, SLT); familiarity with fault models and EDA DFT tools; Master's/PhD and 10+ years preferred.
ATE, MBIST, JTAG, System Level Test (SLT), Synopsys, Design Compiler, DFT Max, Siemens EDA, Tessent, TestKompress, IEEE 1149.1, IEEE 1687, BSDL, STIL, ATPG, iJTAG, TAP
3mo
Save
Mark Applied
Hide
SOC Architect
Santa Clara or Cambridge or France or Oregon or Boston
$254k-$311k/yr OnsiteFull Time
10+ YOEMS or PhD in Computer Science / Computer Architecture; 10+ years in SoC architecture; 5+ years in engineering teams; experience in SoC design flow, architecture, and performance modeling; CPU architectures, power management, platform hardware, OS, drivers, and firmware.
1mo
Save
Mark Applied
Hide
Sr. Principal Engineer, SoC Architect
San Jose, California, United States
$250k-$304k/yr OnsiteFull Time
15+ YOE15+ years in SoC/system architecture; strong high-speed I/O and interconnect knowledge; leadership, cross-functional collaboration.
PCIe, PCIe Gen5, PCIe Gen6, CXL/UCIe, HBM, SerDes, Ethernet, USB, Memory interconnect, Interconnect
2mo
Save
Mark Applied
Hide
SoC Architect
San Jose or United States
$175k-$350k/yr HybridFull Time
18+ YOEBachelor's/Master's/PhD in EE/Computer Engineering or related; 18+ years in SoC/system architecture; expertise in high-speed IO, data movement, performance modeling, and cross-functional collaboration.
UCIe, PCIe, CXL, UALink, ESUN, Ethernet
3w
Save
Mark Applied
Hide
Senior Engineer, SoC Architecture – Memory Subsystem and Interconnect
Mountain View, California, United States
$159k-$218k/yr OnsiteFull Time
7+ YOEBSc/Masters/PhD in CS/Engineering (or equivalent), >7 years experience in fabric/system cache/DRAM controller architecture, 3+ years in SoC/ASIC design, knowledge of memory controllers, ARM bus protocols, JEDEC memory standards.
BookSim Simulator, Platform Architect, ARM, ACE, AXI, AHB, JEDEC, LPDDR, DDR, HBM
3w
Save
Mark Applied
Hide
SoC Architect
Santa Clara, California, United States
$175k-$265k/yr HybridFull Time
d-Matrix: Develops high-performance semiconductor chips for generative AI inference.
5+ YOEMS in CS/ECE or related with 5+ years in SoC/compute architecture; expert in AI SoC architecture, performance modeling, ML (transformer/CNN/RNN), workload analysis; strong Python; C/C++ preferred; leadership in architecture delivery.
Python, C, C++
2mo
Save
Mark Applied
Hide
Senior Staff SoC Design Engineer
Santa Clara, California, United States
$134k-$201k/yr OnsiteFull Time
5+ YOEBachelor's in CS/EE with 5-10 years; or Master's/PhD with 3-5 years; strong SystemVerilog RTL; SoC integration; AMBA AXI; scripting (Python/Tcl).
SystemVerilog, AMBA AXI, Python, Tcl, Synthesis, CDC/RDC, UCIe, UALink
1w
Save
Mark Applied
Hide
Lead SoC Design Engineer
Los Altos, California, United States
OnsiteFull Time
Anodize: Developing next-generation personal computing hardware and consumer electronics.
10+ YOE10+ years developing complex ASICs; Bachelor's in EE/CE (or equivalent); deep knowledge of AMBA protocols, Verilog/SystemVerilog/SVA, SDC timing constraints, multi-power-domain design and UPF; experience with ASIC CAD flows.
AMBA AXI, AXI-S, APB, Verilog, SystemVerilog, SystemVerilog Assertions (SVA), SDC, STA, Lint, CDC, RDC, LEC, UPF, UCIe, DDR, Arm
2mo
Save
Mark Applied
Hide
SOC Architect
San Francisco, California, United States
$266k-$445k/yr OnsiteFull Time
Define architecture for custom SoCs; lead hardware/software co-design; deep AI/ML accelerator knowledge; cross-functional leadership.
RTL, ASIC, SoC design, edge AI
3w
Save
Mark Applied
Hide
Lead SoC Architect - India
Sunnyvale or India
OnsiteFull Time
10+ YOERequires Bachelor's or Master's in EE/CE/CS, 10+ years SoC/ASIC experience, expertise in SoC subsystems (CPU/GPU/NPU, NoC, memory, PCIe), C/C++/SystemC modeling, RTL knowledge, and on-site presence in Sunnyvale.
C, C++, SystemC, Linux
1mo
Save
Mark Applied
Hide
AI SOC Architect
Los Altos, California, United States
OnsiteFull Time
10+ YOEBachelor's in EE/CE (Master's preferred), 10+ years SoC/compute architecture experience with RISC-V and AI acceleration, expertise in multicore clusters, memory hierarchies, performance modeling, and strong communication skills.
RISC-V, AXI, UALINK, HBM, RTL
Explore Jobs
Expand Your Job Search
Top Cities Near Berkeley for Soc Engineer
- Soc Engineer jobs in San Jose, CA
- Soc Engineer jobs in San Francisco, CA
- Soc Engineer jobs in Oakland, CA
- Soc Engineer jobs in Fremont, CA
- Soc Engineer jobs in Santa Rosa, CA
- Soc Engineer jobs in Hayward, CA
- Soc Engineer jobs in Sunnyvale, CA
- Soc Engineer jobs in Concord, CA
- Soc Engineer jobs in Santa Clara, CA
- Soc Engineer jobs in Vallejo, CA
- Soc Engineer jobs in Fairfield, CA
- Soc Engineer jobs in Antioch, CA
- Soc Engineer jobs in Richmond, CA
- Soc Engineer jobs in Daly City, CA
- Soc Engineer jobs in San Mateo, CA
- Soc Engineer jobs in Vacaville, CA
- Soc Engineer jobs in San Leandro, CA
- Soc Engineer jobs in Livermore, CA
- Soc Engineer jobs in Tracy, CA
- Soc Engineer jobs in Redwood City, CA